Tool base consolidates for 16 nm FinFET design at TSMC

April 16, 2014 // By Graham Prophet
In what is clearly a co-ordinated announcement orchestrated by foundry TSMC, each of Mentor Graphics, Cadence and Synopsys have stated that their tool chains for TSMC’s 16-nm FinFET process have achieved certified status. (image; Synopsys’ realisation of FinFET parasitics)

Mentor Graphics announces that its IC design-to-silicon solution has achieved certification for TSMC’s Design Rule Manual (DRM) and SPICE model version 1.0 for its 16nm FinFET process. The certification includes tools in the Calibre physical verification and design-for-manufacturing (DFM) platform, as well as the Olympus-SoC place and route system, the Pyxis custom IC design platform, and Eldo SPICE simulator. Mentor also demonstrated a complete 16nm FinFET digital flow using the Olympus-SoC and Calibre products and the ARM Cortex-A15 MPCore processor as the validation vehicle. The Mentor 16nm solutions are available now to support customers as they transition from test chips to full production 16nm FinFET design efforts.

The Olympus-SoC place and route system enables design closure with support for all 16nm FinFET double patterning (DP), DRC and DFM rules, fin grid alignment for macros and standard cells, and Vt min-area rules support. The new flow also supports low-voltage hold time fixing, interconnect resistance minimisation, signal EM fixing, MiM Cap extraction to address timing impact, and enhanced pin accessibility and routability.

The Calibre nmDRC platform ensures designs meet process requirements. The SmartFill capability in Calibre YieldEnhancer, along with the other Mentor DFM products, Calibre LFD and Calibre CMPAnalyser, were enhanced to meet TSMC-specified requirements for filling, lithography, and CMP simulations for 16FF.

The TSMC 16nm design kit offering for Mentor provides reliability checks based on the Calibre PERC product. This enables customers to analyse and correct issues such as electrostatic discharge (ESD) and latch-up at both IP and full chip level using a common platform and set of checks regardless of the IP source.

To ensure accurate circuit simulation of FinFET devices, Mentor collaborated with TSMC on enhancement and certification of the high-performance Calibre xACT 2.5D and 3D extraction product, and FinFET device models in the Calibre nmLVS product.

The Pyxis custom IC design platform is extended to handle fin grids and provide a fin grid display, and to support guard rings, MOS abutment rules and design rule-driven (DRD) layout. The Eldo simulator has been upgraded to provide accurate FinFET device and circuit level modelling based on the latest BSIM-CMG and TMI models from TSMC.

Mentor Graphics;

next; Cadence’s announcement on 16nm at TSMC;