Toshiba packs 256 Gbits of flash on a chip, in 48-layer 3D structure

August 05, 2015 // By Graham Prophet
Toshiba has disclosed its latest generation of BiCS FLASH, its three-dimensional (3D) stacked cell structure flash memory. The claims a record with the first 256-Gigabit 48-layer BiCS FLASH device, which uses three-bit-per-cell (triple-level coding or TLC).

BiCS FLASH uses a 48-layer stacking process exceed the capacity of mainstream two-dimensional NAND flash memory, while (Toshiba asserts) enhancing write/erase reliability endurance and boosting write speeds. The 256 Gb device is suited for typical NAND-flash applications, including consumer SSDs, smartphones, tablets, memory cards, and enterprise SSDs for data centres.

Since announcing the prototype BiCS FLASH technology in June 2007, Toshiba has continued development towards optimisation for mass production. To meet further growth in the flash memory market in 2016 and beyond, Toshiba is bringing forward migration to BiCS FLASH by rolling out a product portfolio that concentrates on large capacity applications, such as SSDs.

"From day one, Toshiba's strategy has been to extend our floating gate technology, which features the world's smallest 15nm 128Gb die," a Toshiba spokesman said, "Our announcement of BiCS FLASH, the industry's first 48-layer 3D technology, is very significant in that we are enabling a competitive, smooth migration to 3D flash memory – to support the storage market's demand for ever-increasing densities."

Toshiba has a long-standing commitment to flash memory, and is currently readying for mass production of BiCS FLASH in the new Fab2 at its Yokkaichi Operations, its production site for NAND flash memories. Fab2 will be completed in the first half of 2016.