Toshiba starts sampling of 64-layer 3D flash memory at 256 Gbit density

July 27, 2016 // By Graham Prophet
Toshiba Corporation has disclosed the latest generation of its BiCS FLASH three-dimensional (3D) flash memory with a stacked cell structure, a 64-layer device that it claims as the first to start sample shipments.

The new device incorporates 3-bit-per-cell (triple-level cell, TLC) technology and achieves a 256-gigabit (32 gigabytes) capacity, an advance that underscores the potential of Toshiba’s proprietary architecture. Toshiba continues to refine BiCS FLASH, and the next milestone on the development roadmap is a 512-gigabit (64-gigabytes) device, also with 64 layers.

 

The new device succeeds the 48-layer BiCS FLASH [to which the above graphic relates], and its 64-layer stacking process realizes a 40% larger capacity per unit chip size than 48-layer stacking process, reduces the cost per bit, and increases the manufacturability of memory capacity per silicon wafer. 64-layer BiCS FLASH can meet demanding performance specs, and the new device will be used in applications that include enterprise and consumer SSD, smartphones, tablets and memory cards.

Toshiba announced the first prototype 3D flash memory technology in June 2007; the company is actively promoting BiCS FLASH to meet demand for larger capacity with smaller size. Toshiba will produce the new 64-layer BiCS FLASH in the New Fab 2 at Yokkaichi Operations, which was officially opened earlier this month, and mass production of 64-layer BiCS FLASH is scheduled to start in the first half of 2017.

 

Toshiba; www.toshiba.semicon-storage.com