Ultra-low-jitter clock generators for comms infrastructure

October 01, 2015 // By Graham Prophet
Texas Instruments has added a family of clock generators that provides jitter of 100 femtoseconds (fsec) and flexible pin control options: compared to conventional reference clock solutions, these clock generators’ jitter performance enables system designers to optimise system timing margins and bit error rate (BER) to reduce data transmission errors.

LMK033x8 clock generators also offer versatile features to reduce design cycle time by facilitating easy prototype design and evaluation. The parts offer;

Jitter performance enabling flexible jitter budgeting: one, or two, high-performance PLLatinum fractional-N phase-locked loops (PLLs) with eight outputs enable ultra-low jitter performance of 100 fsec root mean square (RMS) over multiple integration bandwidths (1 kHz-5 MHz and 12 kHz-20 MHz). Designers can take advantage of the ultra-low jitter to improve their system BER and increase the reliability of their telecommunications infrastructure equipment.

Flexible, simple configuration: a unique pin-mode control feature enables designers to select from 71 pre-programmed frequency startup plans compared to one-time programmable memory offered by alternatives. Integrated EEPROM supports customisation, while the I²C interface gives system designers complete control of device configuration.

Reduced design cycle time: glitchless fine/coarse frequency margining enables designers to simplify the stress and compliance testing of their systems during design verification and process verification (DVT/PVT) of prototypes.

Immunity to supply noise: integrated low-dropout regulators (LDOs) provide immunity to power-supply noise without requiring complex filter designs.

Evaluation modules (EVMs) comprise the LMK03328EVM, and the LMK03318EVM that will be available in 4Q 2015. TI’s WEBENCH Clock Architect tool simplifies the design process for the LMK033x8 family; the tool can recommend a single- or multiple-device clock-tree solution from a broad database of devices to meet system requirements. It features PLL filter design, phase-noise simulation, and the ability for designers to optimise clock-tree designs for their performance and cost requirements.

LMK033x8 clock generators come in a 7 x 7-mm quad-flat no-lead (QFN) package. The LMK03328 dual-PLL eight-output clock generator is priced at $10.00, and the LMK03318 single-PLL eight-output clock generator will be $7.50 (both 1000).

TI; www.ti.com/lmk033xx-pr-eu

Support materials from TI include; blog posts about clock and timing; an LMK033x8 demonstration video ; and app notes, “ Clocking high-speed serial links using LMK03328 .” and “ Frequency margining using TI’s high-performance clock generators .”