The clock synthesiser uses a flexible delta-sigma modulator and a very wide-ranging VCO in a PLL block that has been optimised to be extremely power efficient. With a core current consumption of just 20 mA, these parts dissipate 60% less power than equivalent devices. The PLL can operate from either an input system clock or a crystal, and incorporates both an integer divider and a high-resolution (<1 Hz) fractional divider for increased flexibility to generate any clock frequency. Additionally, up to four different frequency multiplier settings can be stored, allowing for different application configurations and providing BOM savings compared to multiple synthesisers. The XR81112 is configurable for LVCMOS, LVDS or LVPECL outputs.
Exar's Universal Clocks deliver extremely low, sub-200 fsec, output phase noise jitter as integrated over a 1.875 MHz – 20 MHz bandwidth. This spans the requirements of most WAN and LAN systems and supports communications standards including: 10 GHz Ethernet, 2.5 GHz and 10 GHz SONET/SDH/OTN, xDSL and PCIe, as well as many other synchronised clock system applications. The XR81112 is available as a pre-configured device or can be optionally programmed by 3rd party programming houses. It costs $7.00 (1000).