Ultra-low power IP subsystem enables integration of sensor functions into SoCs

July 31, 2013 // By Graham Prophet
Synopsys has announced its DesignWare Sensor IP Subsystem, a complete and integrated hardware and software solution for sensor control applications that will form part of an SoC (system on chip) design.

An integrated, pre-verified hardware and software IP subsystem consists of a power- and area-efficient ARC 32-bit processor, digital and analogue interfaces, hardware accelerators, software library of DSP functions and I/O software drivers. It is highly configurable with tightly integrated peripherals and dedicated hardware to maximise sensor processing efficiency.

More than ten configurable hardware accelerators reduce memory footprint and decrease power consumption by a factor of 10 compared to equivalent discrete component implementations: a library of off-the-shelf software DSP functions, including mathematical, filtering, matrix/vector and decimation/interpolation, speeds application software development. The complete IP can occupy as little as 0.01 mm 2, and can use less than 4 µW/MHz, in a 28-nm process.

The IP subsystem is optimised to process data from digital and analogue sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power. The fully configurable subsystem consists of a DesignWare ARC EM4 32-bit processor, digital interfaces, analogue-to-digital data converters (ADCs), hardware accelerators, a comprehensive software library of DSP functions and software I/O drivers. It is a complete and pre-verified solution that meets the requirements of a broad range of applications such as smart sensors, sensor fusion and sensor hub.

The DesignWare Sensor IP Subsystem features the power- and area-efficient DesignWare ARC EM4 32-bit processor core, which includes custom extensions and instructions that support application-specific hardware accelerators and tightly integrated peripherals. The subsystem includes multiple configurable GPIO, SPI and I 2C digital interfaces for off-chip sensor connections as well as ARM AMBA AHB and APB protocol system interfaces to ease integration into the full SoC. The analogue interfaces include low-power high-resolution ADCs that efficiently digitise sensor data for the processor. The sensor subsystem's HAPS FPGA-based prototyping solution enables immediate software development and provides a scalable platform for rapid full system integration and validation. Synopsys also offers SoC integration services to help customers integrate the subsystem into their chip or customise