UltraSoC (Cambridge, United Kingdom), provider of on-chip monitoring and analytics solutions for complex systems-on-chip (SoCs), has released enhancements to its product, allowing users to integrate legacy signal-based systems with the company’s message-based architecture. The new capabilities are particularly beneficial to SoC designers working with the range of processor cores from ARM and its associated debug system, CoreSight.
UltraSoC’s vendor-independent technology allows engineering teams to understand what is really happening inside the SoC, non-intrusively and at wirespeed. This enables them to control and monitor the behaviour of any on-chip structure, be that a processor, third-party block, custom logic or bus – in active operation. Such capabilities are essential for the engineers whose task it is to ensure that the device and its software are functioning correctly. The added features provide a bridge between UltraSoC’s infrastructure and traditional signal-based systems such as CoreSight, so UltraSoC provides truly universal debug capabilities with faster, more reliable development and performance profiling.
UltraSoC CEO Rupert Baines comments, “Modern SoCs are massively sophisticated, and are just too complex for architects to fully understand or predict using traditional debug techniques. The world has moved away from a signal-based approach to message-based architectures: the success of network-on-chip (NoC) companies such as Sonics, Arteris and NetSpeed is testimony to this. But customers have made substantial investments - both in terms of dollars and in intellectual property - in the older signal-based technologies. We bridge that gap, with a ‘smart’ vendor-neutral approach that helps developers who employ IP from several different suppliers, or who need more than simple CPU monitoring to debug and optimise their designs.”
By interworking smoothly with signal-based products such as CoreSight, UltraSoC enables a holistic and fully-featured solution for on-chip debug and performance analysis, including monitoring of custom logic; transactions on common bus structures such as AXI and OCP; monitoring of processors, including ARM, MIPS and XTensa cores; support for custom logic; deadlock detection; optimisation; and generation of meaningful performance metrics such as latency and best/worst/average utilisation. The UltraSoc functionality is non-intrusive, operates at system speed and integrates functionality to intelligently filter signals to reduce trace bandwidth and efficiently highlight problems.