TiePie Engineering's latest model, HS5-540, uses what the company calls CDS (Constant Data Size) architecture. It's closer to a traditional sampling AWG than to a DDS architecture. But, it differs in that its clock can change frequency to change sampling rate up to 240 Msamples/sec. Sampling AWG's may use a fixed clock frequency and then change sample rate by dividing the clock. In its recent product release, TiePie stresses how the CDS architecture differs from DDS, but I asked how it also differs from a traditional sampling AWG.
"The CDS technology is different from a traditional non-DDS AWG, in the area of the sampling clock generation," said TiePie's Erik Tigchelaar. "Our clock can be set at any frequency and can be changed with very small steps and has very little jitter, making it possible to generate very accurate and stable signals." Jitter is specified as less than 50 psec rms.
The image below shows how skipping clock signals with a DDS AWG can result in missing samples. The lower trace shows spike that a DDS architecture might miss.
AWG basic specs for the HS5-540 include; total harmonic distortion - 0.04 %; Jitter - 20 psec; signal frequency range - 40 MHz; memory size - 64 Mbytes; rise time - 8 nsec.
The HS5-540 is, of course, an oscilloscope; sample rate: 500 Msamples/sec in 8 bit or 12-bit mode; resolution - 8, 12, 14, or 16 bits (sample rate slows as resolution increases); analogue bandwidth: 250 MHz; 2-channels. Base price is €1346. TiePie Engineering's other HS5 models now also feature the CDS architecture.
TiePie Engineering, www.tiepie.com/HS5