“The development towards FPGA based board designs is also accompanied by more and more high-speed I/O, difficult to test by traditional metrology due to continuously decreasing physical access. Our new solution addresses this very problem”, says Heiko Ehrenberg, Technology Officer for Embedded System Access for Goepel electronics in the USA. “Because of high automation level, the high-speed I/O’s FPGA parameters can be interactively defined, and become immediately effective without design synthesis, i.e. users can directly validate the influence on transfer quality. Furthermore, signals received in the silicon are recorded and visualised, which enables unaltered measurement results.”
The new generator is another option in the System Cascon integrated JTAG/Boundary Scan software platform, enabling automatic generation of complete application scripts for FPGA embedded HSIO test instruments. These are chip-dependent instrument selections, establishment within an FPGA, addressing, configuration, procedural control, qualification of generated data and graphical eye visualisation.
The AAPG connects ChipVORX model integrated instrument information with the intrasystem data base for structural and functional UUT (unit under test) description and protocol-specific user guidelines for configuration of the target FPGA’s high-speed I/O channels. The fully automatically generated script is based on the System Cadcon integrated standard language CASLAN (CAScon LANguage) and can be executed on each run-time station without additional options. Gang applications are also supported.
Chip embedded Instruments are permanently integrated or temporarily implemented test and measurement functions (T&M) in an integrated circuit. Virtually, they are the counterpart to external T&M instruments as they don’t require invasive contacting by means of probes or nails. Hence, the problem of signal distortion in high-speed designs by parasitic contacting effects is omitted. Chip embedded Instruments are part of the so-called Embedded System Access (ESA) technologies that are currently the most modern strategy for validation, test and debug as well as programming of complex boards and systems. They can be utilised throughout the entire product life cycle, enabling improved test coverage at reduced costs.