Verification solutions for the RISC-V open ISA

March 10, 2017 // By Graham Prophet
Codasip (Brno, Czech Republic), provider of IP for the RISC-V processor architecture, together with T&VS (Test and Verification Solutions), verification services provider for semiconductor IP, hardware and software, has announced a collaboration to accelerate the verification of products based on the Codix-Bk series of RISC-V compliant processor cores.

The partnership ensures companies can be confident selecting the precise RISC-V configuration they require. The combination of Codasip’s IP generation technology and the highly-automated T&VS validated verification flows means that even the most specific configurations can be quickly verified to the highest standards. Such a capability will be essential to fully exploit the flexible, open-source RISC-V instruction set architecture (ISA).

 

“I am extremely pleased to see this robust solution coming into place.”, said Rick O’Connor, Executive Director of the RISC-V Foundation. “It is further evidence of the healthy and rapid growth of the RISC-V ecosystem.”

 

Interest in the RISC-V ISA has grown; the principal advantages for design teams are the non-proprietary nature of the ISA, the availability of implementations and infrastructure from a range of suppliers and the design freedom allowed by the RISC-V standard. However (notes Codasip) this flexibility poses a challenge for verification. Since a wide range of function/power/performance variants is possible, there is no off-the-shelf set of RISC-V validation tests, no single verification testbench, nor even a single verification flow, to fully verify an implementation.

 

RISC-V verification becomes a challenge as particular functionality/performance combinations that a design requires are not available in an off-the-shelf configuration. In these circumstances someone has to produce a variant of the design (RTL + Software Development Kit (SDK)) and verify it. This is clearly a challenge for RISC-V providers, whether they are Silicon IP (SIP) companies or service organizations within large companies.

 

“In order to thoroughly and quickly verify a new variant of the RISC-V it is crucial to have a strategy that covers the whole RISC-V family, both at the architectural and

micro-architectural levels.” said Mike Bartley, CEO, T&VS, “Working with Codasip removes the guesswork from our strategy since they are able to generate new variants of the cores very rapidly, meaning that we are prepared for just about anything.”

 

Codasip; www.codasip.com

 

T&VS; www.testandverification.com