Verification update at DVCon Europe 2016: registration deadline approaching

September 26, 2016 // By Graham Prophet
This week (commencing 26th September) sees the advance registration deadline for the 2016 Design and Verification Conference in Europe – DVCon – that takes place in Munich on October 19th and 20th. The Conference is sponsored by the Accellera System Initiative, and is accompanied by an exhibit area. The full and finalised conference programme has now been published.

DVCon styles itself as the foremost event for verification technologies and techniques in Europe and as such, its content is centred on the concerns of the European industry. EDN Europe spoke to Intel’s Oliver Bell, General Chair, from Intel), Infineon’s Matthias Bauer, Program Chair and NXP’s Martin Barnasconi, Past Chair to discuss the particular areas of focus of this year’ proceedings (individual remarks aren’t attributed here).


Major areas of interest include UVM, virtual prototyping – and a significant amount of added content on verification of mixed signal designs, rather than purely digital systems. In the same vein – reflecting the focus on the concerns of the European design base – there is an invreased attention to functional safety. This, unsurprisingly, is largely driven by and addresses the concerns of the automotive sector, who make up the largest single sector of the audience. Attendance, overall, has has been growing and the organisers anticipate over 300 delegates for the 2016 event. They (the organising committee) have noted a demand for training and practical guidance, and have responded by constructing this year’s agenda with a increased proportion of tutorial and “hands-on” content. Similarly, there will be no poster sessions but instead, a series of short-format presentations that are termed ‘lightning’ session, to provide a quick update on a very specific topic.


All of today’s verification ‘hot topics’ are covered. UVM gets, say the conference organisers, an emphasis on the ‘U’ (universal), looking at its expanded usage for whole-system verification. TLM, formal methods, IP verification, and a ‘special day’ examination of trends in the use of SystemC, are all scheduled for both regular-session and tutorial treatment. Virtual prototyping, in particular, gets an extended slot in the programme.


Naturally, there are sessions presented by the “EDA heavyweights”; Cadence lends its name to a tutorial on ISO 26262, which according to the session headline, “changes everything”. And Mentor’s name is to be found