Virtual design platform supports coding for Altera Arria 10 SoC FPGAs

November 05, 2015 // By Graham Prophet
Mentor Graphics' Vista virtual platforms for the Arria 10 system-on-chip (SoC) FPGA are fully functional simulation models of processor subsystems and peripherals offered as freely downloadable pre-built binaries.

The models accelerate embedded software development across the entire product life cycle for, Mentor says, significant time-to-market and product development cost savings. Linux runtime support is available from targeting the Arria 10 binary virtual platform. The combination of the Vista virtual platform and Linux makes creates a software-based development and test platform for embedded software engineers.

The Vista virtual platforms enable embedded engineers to begin development and debug for pre-production devices such as the Stratix 10 FPGA well before first silicon availability. The Virtual Platform binaries can be installed and run together with a pre-built Linux image on a host PC. In addition, a model of custom functions in the FPGA fabric can be linked to the virtual platform for system-level simulation. The virtual platforms support both bare-metal/Real-Time Operating System (RTOS) and Linux operating system environments for software execution and debug on multi-core configurations of Altera SoCs. Vista virtual platforms offer technologies including deep, non-intrusive access for software and hardware debug and profiling to substantially improve debug and analysis practices.

Chris Ballough, Altera senior director of marketing comments, “Our technology partnership with Mentor lessens our customers' risks, accelerating embedded system development by identifying design issues that would be difficult or too late to find in the physical hardware.”

Mentor Graphics will provide virtual platforms to support the Stratix 10 product family in the near future.

The Vista virtual platforms are integrated with the Sourcery CodeBench Virtual Edition and Analyzer tool to provide capabilities that include the visibility and control to debug and analyse complex software/hardware interactions and the ability to optimise the software to meet final product performance and power goals.

Using the Vista Architect tool, hardware and system engineers can gain access to the Altera hardware platform source and freely customise and manipulate the SoC and FPGA models. This capability is important to test, analyse, and explore various hardware configurations, peripherals alternatives, memory hierarchies, and resource utilisation.