VirtuosoNext RTOS maximises metrics with Sundance’s DSP board

February 22, 2017 // By Graham Prophet
The combination of OS and OpenVPX board forms an ultra-high bandwidth processing platform suited for computation and bandwidth-intensive high-reliability and safety-critical applications

Sundance Multiprocessor Technology (Chesham, UK) has collaborated with Altreonic to port its multicore VirtuosoNext Designer embedded RTOS to Sundance’s VF360 3U OpenVPX single board computer (SBC) (above), that integrates a Texas Instruments C6678 Keystone multicore DSP alongside an Altera Stratix V FPGA.

VirtuosoNext Designer is Altreonic’s fifth generation embedded RTOS. It delivers performance and productivity gains due to its extremely compact kernel size that can even fit in the on-chip caches. It also supports a modelling and code generation environment that makes parallel and concurrent programming easy to achieve. By generating code as a static image, it eliminates many of the runtime errors that can occur with a more traditional dynamic RTOS. Its packet switching architecture also reduces typical pointer errors providing extra robustness. An ARINC-653 interface is on the road map although the native VirtuosoNext support is more aimed at hard real-time behaviour.


Coupled with the on-board multicore DSP, which runs at 1.25 GHz and delivers up to 224 GFlops from its eight cores with a peak bandwidth of 16 Gbytes/sec, VirtuosoNext Designer maximises the power of the VF360 SBC. Altreonic comments that its OS exploits the hardware of the SBC and facilitates parallel programming thereby enabling computation and communication tasks to be implemented concurrently. Support for the MPU fully isolates the cores from each other for safety and reliability.”


The VF360 SBC features a VITA65 OpenVPX compliant backplane interface, which provides plenty of bandwidth for board-to-board communication in the form of three 4-lane PCI Express fat pipes and 10 multi-gigabit transceivers for more generic protocols such as 10Gb Ethernet, Serial Rapid IO (SRIO), Aurora (RocketIO) and SerialLite II. It also acts as a VITA 57 FMC carrier to provide a modular solution that accommodates a wide range of I/O requirements.


The Stratix V FPGA connects to the multicore DSP, backplane and FMC site and facilitates the integration of safety-critical and commercial IP cores such as