Wafer-level packages eliminate “under-bump metallisation” for under 0.5 mm profile

April 08, 2015 // By Graham Prophet
Altera and TSMC, for the former’s MAX 10 FPGA products, are extending their collaboration on embedded flash technology at 55 nm with what they are calling a “unique packaging innovation”

The two companies have produced “UBM-free” (under-bump metallisation-free) WLCSP (wafer-level chip scale packaging) technology that provides enhanced quality, reliability and integration for Altera’s MAX 10 FPGA products.

This approach results in an extremely thin package height of less than 0.5mm (including solder ball) for applications where space is at a premium, such as sensor applications, small form-factor industrial equipment, and portable electronics. Other benefits include a better than 200% improvement in board-level reliability compared to standard WLCSP, while enabling a large die size envelope and high package I/O count, targeting applications such as wireless LAN (WLAN) and power management ICs (PMIC). Copper routing capability and inductor performance are also said to be enhanced.

MAX 10 FPGAs are single-chip, small-form-factor programmable logic devices with densities from 2k– 50k logic elements (LEs), using either single or dual-core voltage supplies. MAX 10 FPGA devices are built on TSMC’s 55nm embedded NOR flash technology that enables instant-on functionality. Altera is currently sampling MAX 10 FPGA products with the new WLCSP packaging. There are 81-pin and 36-pin WLCSP packages available. An overview of both V81 and V36is at www.altera.com/max10-product-table

Altera; www.altera.com/max10-package