The focus of the discussions as on large format fan-out packaging, or the necessity that OSATS felt, under yield and packaging cost pressures, to move from Fan-Out Wafer-Level-Packaging (FO-WLP) to Fan-Out Panel-Level-Packaging (FO-PLP).
First highlighting the market drivers for FO-WLP, TechSearch International's president E. Jan Vardaman pointed out how year-on-year mobile devices become thinner and thinner by adopting an increasing number of wafer level packages for their electronic content.
She illustrated this with seven generations of iPhones, thinning from around 12 mm to 7 mm while increasing their WLP content from 2 dice to over 26 dice.
iPhone Trends: Increasing Number of WLPs. Source: TechSearch International, Inc.
The conventional WLPs trends, she said, include higher I/O counts and larger dice. And together with shrinking geometries, the number of I/Os per die dramatically increased over the years from a few dozens to well over 400, calling for multi-die packages or a move to larger FO-WLP where the I/Os can be distributed not only underneath the die but at the package’s periphery (like extra margins surrounding the die).
Typically, FO-WLP benefit from the same thinness (under 0.4 mm) but can integrate multiple dice from different technology nodes, as well as some passives. Nanium offered an example by moulding together two active dice and 10 surface-mounted passives within a 9 x 8 mm package.
Nanium's multiple die Fan-Out package integration with passives.
According to TechSearch, FO-WLP could reach over 1.8 billion units per year in 2019, versus less than 300 million packages shipped in 2014. But then, if the trend is to continue, the real-estate on reconstituted wafers will become the limiting factor for optimised larger package integration and cost efficiency, since the piece count remains limited or is even reduced (as the packages grow) on a wafer-like substrate.
As the declining average selling price for end products creates further price pressure, it drives OSATS to develop lower cost package options too, moving to large area packaging beyond today’s wafer sizes. "This is where the wafer fab side, back end assembly, and PCB segments are merging" she said.
Citing a few examples of panel-sized FO-WLP R&D efforts up to 610 x 457 mm, Vardaman concluded that panel-based processing has a promising future despite the numerous technical challenges it brings with it.
These challenges, just to name a few, include large panel manipulation (new infrastructures moving the dice from wafer-level processing machines to larger panel-capable equipment), die placement accuracy across large panels, panel warpage and new dispensing processes altogether to achieve sufficient moulding uniformity and planarity.