When I first learned to design digital electronics and layout a PCB, I was taught to put all the 74-series chips and the microprocessor in neat rows, and the rule of thumb was to add a single 0.1 µF ceramic capacitor for decoupling to each device, and sometimes adding an additional 1 µF tantalum or electrolytic for the micros in parallel. I never worried too much about getting power to each device - using a 20 or 30 mil trace was enough for a chip that never drew more than 100 mA, along with the classic interdigitated +5V/GND “grid”. Of course, power electronic designs are a whole different ball game. And I always took a lot more time, care and planning with power supply and amplifier designs - making sure to use proper (star) grounding and keeping high-current loops as tight as possible.
Some of this was more than 20 years ago now, and of course there has been a lot of development in the decoupling and power network topic since then. More elaborate and carefully placed decoupling schemes have to be designed for each new silicon process node, each new chip package generation and for each new PCB design as they become more densely packed with parts than ever. It's getting difficult to find room for all the “rule of thumb” decoupling caps! And with BGA packaged devices down to 0.4 mm pitch, that meanwhile draw several amps of current during use, it’s getting really difficult to plan and design a good power network on the PCB. Whether we like it or not, Power Integrity is a challenge that all PCB designers and engineers have to address.
Power Integrity is talked about a lot these days. But a lot of the talk is really on the signal integrity side - I call it AC power integrity, which is really about the impedances of the power network at high frequencies.