What about DC Power Integrity? - Part 2

September 03, 2014 // By Benjamin Jordan, Altium
It’s getting really difficult to plan and design a good power network on the PCB. Whether we like it or not, Power Integrity is a challenge that all PCB designers and engineers have to address.

Part 1 of this article outlined the basic principles of ensuring power integrity (PI) on a PCB; at symptoms that reveal your board may have a PI problem; and at extracting some key figures from active device data sheets; Part 1 is here.

Monitoring tools for embedded systems

One useful function offered by modern embedded tools is the ability to monitor power consumption in concert with debugging code. Various means of measuring power are provided.

For example, the STM32429IG-EVAL board from ST Micro, which uses a variant of the ARM processor mentioned in Part 1 of this article, is designed with a jumper in place for the VDD rail to the CPU. The intent is that while you are developing and debugging source code you can be measuring the current being supplied to the CPU:

1. Set a breakpoint at the beginning and end of the code routine of interest.

2. Enable the oscilloscope trigger on the current measurement probe on JP2.

3. Step into the routine, capturing the current waveform on the 'scope.

4. Repeat for all routines of interest, taking note of the current requirements.

This way, you can get a clear picture of how the source code is affecting power consumption, and even decide how to modify code to optimise or limit power usage.

Similar tools are available for monitoring FPGA development flows. Figure 4 shows the power monitoring capability of the NanoBoard FPGA development board. In this example I am running the C-to-Hardware reference design that spins a graphical cube in 3D. I can switch between processing the matrices for transformation in software and FPGA hardware, and compare the power consumption based on how the job is done. Similar tools can be found with FPGA vendor development boards as well.

Figure 4. Monitoring power consumption during FPGA/Software debug of a System on Chip design.

Working with DSO or PC-based instruments along with the embedded debug tools even give you an edge in developing lower power code. Figure 5 shows this in action with “PowerScale” (from Hitex, which works alongside Altium's TASKING C/C++ development tools).

Figure 5. Using high-speed current probes with the development board.

In this case it’s easy to measure peak and average currents required by your source code over the software execution lifecycle. But what can you do to ensure that your custom PCB design can cope?

So what’s it to do with DC Power Integrity?

Modern designs are complex, and with limited space to design the power network on the PCB, and with ever shrinking device packages, it’s getting hard to use the old brute force “plenty of copper” approach to providing power to these devices. Knowing about these techniques will be key in using a multi-pronged approach to solving power integrity bottlenecks at the PCB design level also.

A PCB fuse trick?

Before I dive in, however, let me share a little story. When I was a wet-behind-the-ears college student, I had a part-time job doing PCB design and assembly at a “ma and pa” electronics company in my hometown. They were really cool people, and I learned a great deal about PCB design and hand prototyping, design for assembly, and testing from the proprietor. I was impressionable in those days, and one thing he impressed me with at the time was how he used to design fuses into his PCBs with thin trace segments, and a component land pattern for a real fuse should the PCB trace need “replacing”. The fuse was apparently rated at 2A, and was a 10 mil (0.010 in./0.25 mm) width in standard 1oz. copper. I wondered if he had some magic formula or if he had empirically chosen the width. He wouldn’t tell me...

There are several factors at work in the PCB which can undermine longevity or performance, not the least of which is temperature change. We normally do consider temperature rise, because what we really want to know is how to prevent failure or damage due to overheating. But more generically, large temperature swings can also limit the useful life of the product due to other thermo-mechanical stresses.

next; polygon ‘necks’...