Part one is here.
Simply taking an architecture like that shown in Figure 1 ( see part 1 of this article ) and directly integrating it into a system on chip will not result in a power or cost savings. Power savings come through selecting an efficient architecture that can be optimized for the process on which it is targeted. Architectures like the IF sampling receiver shown involve a lot of high and mid-range frequencies that are difficult to scale on low costs processes and therefore require significant amounts of power be dissipated to support the frequencies required. However, the zero IF architecture as shown in Figure 2 ( part 1 ) works to immediately reduce the frequencies of interest to DC (baseband) allowing implementation of the lowest frequency circuits possible.
Similarly throwing bandwidth at the problem is also inefficient. Architectures like direct RF sampling provide wide bandwidths with a lot of flexibility. However adding bandwidth to a system always adds extra power to the problem as documented by both Walden [Ref. 1] and Murmann [Ref. 2]. Unless the raw bandwidth is required, addressing the problem with bandwidth alone doesn’t provide an economical solution for most receiver applications. Data from these long term studies show two regions of converter development. The technology front documents advances in technology that provide for meaningful increase in core AC performance in the form of dynamic range and bandwidth.
The architecture front documents advances in overall core architecture efficiencies. Typically the curve moves to the right firstly and then upward as designs are optimized. For communications applications, operation tends to be along the technology front where the slope of the line is about 10 dB per decade reduction in converter efficiency as shown in Figure 7. At this slope, doubling the bandwidth results in dissipating about 3 times the power. However, by the time these cores are integrated into