The 32-bit RISC processor offers high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low-power operation with programmable clock speeds. It also includes a 2.4 GHz IEEE802.15.4 compliant transceiver and a mix of analogue and digital peripherals. Receiver operating current (down to 13 mA and with a 0.7 μA sleep timer mode) gives excellent battery life allowing operation direct from a coin cell.
The CPU of the JN5169 is a 32-bit load and store RISC processor. It has been architected for 3 key requirements:
- low power consumption for battery powered applications
- high performance to implement a wireless protocol at the same time as complex applications
- efficient coding of high-level languages such as C provided with the Software Developer’s Kit.
The peripherals support a wide range of applications. They include a 2-wire compatible I²C-bus and SPI-bus which can operate as either master or slave, a 6-channel ADC with a battery monitor and a temperature sensor. It can support a large switch matrix of up to 100 elements, or alternatively a 40-key capacitive touch pad.
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