Wireless-standard-compliant simulation software for RFIC design

January 07, 2014 // By Graham Prophet
The latest release of Agilent's GoldenGate, its RFIC simulation, verification and analysis software, provides RFIC designers with EVM-, BER- and ACPR-type measurements and enables you to quickly analyse and diagnose problem areas in large-signal analysis. It offers a number of new capabilities to reduce simulation time and increase design efficiency.

Advanced wireless standards (Agilent notes) such as LTE Advanced (4G) and 802.11ac (WLAN) put high demands on linearity, bandwidth and noise performance, which is changing the nature of transceiver IC design. GoldenGate 2013 introduces new verification test benches that allow you to easily validate and optimise designs using standard-compliant waveforms and measurements such as EVM/ACLR in transmitters, or sensitivity/desensitisation in receivers.

"RF system simulations using the actual standard-compliant modulated signals in order to fully capture third-order nonlinearities, AM/AM and AM/PM distortions, spectral regrowth, and memory effects are crucial to develop leading-edge RF products targeting advanced wireless standards," said Juergen Hartung, RFIC product manager at Agilent EEsof EDA. "As a result, designers are now able to identify marginal designs early, as well as overdesigns that add costly, unnecessary die area or current consumption."

While GoldenGate is known for its RF circuit simulation performance and robustness, it also provides a host of technologies to explore, analyse and optimize RF circuits early in the design cycle. With this latest release, a new sensitivity analysis has been added that can be applied when analysing RF circuits, even when running large-signal analyses. Enhancements include;

Fast circuit envelope (FCE) model export from GoldenGate to SystemVue, which now includes noise support that is critical for any receiver test (e.g., sensitivity/desensitisation). FCE creates a model that is used in SystemVue to represent the degradation due to the RFIC in system-level simulations without facing much of a performance impact.

Fast yield contributor support in envelope transient and S-parameter analyses, which provides a speed-up of Monte Carlo simulations for process and mismatch variations. It also provides a contributor table to identify root cause devices and/or blocks.

Core solver improvements, such as a new oscillator algorithm, that specifically target high-Q oscillators and high-level transient accuracy control.

Automatic steady-state detection and auto-harmonic estimation within initial transient, which reduces simulation time and increases design efficiency.

A broad range of usability enhancements within the