Xilinx to add DSP cores to Zynq at 20 nm

November 13, 2012 // By Nick Flaherty
Xilinx is planning to add digital signal processor (DSP) cores alongside ARM processors for its next generation of Zynq 'all programmable' FPGA.

High-growth applications for the next generation Zynq family include heterogeneous wireless network radios, baseband acceleration and backhaul, data center security appliances, and embedded vision applications in automotive, industrial, scientific, medical, and Aerospace and Defense markets, all of which will benefit from a hard-wired DSP core. These will sit alongside ARM cores and FPGA fabric.

The bandwidth between the heterogeneous processing system and the FPGA fabric for accelerating key processing functions, as well as next-generation security enhancements.

“The 20nm portfolio will address the exponentially growing programmable imperative, fueled not only by the untenable cost of design, but by the need to continuously infuse more intelligence in every system with maximum adaptability, reuse, and systems integration,” said Xilinx president & chief executive officer, Moshe Gavrielov.

Target applications also include image and video processing including intelligent ‘embedded vision’ for next-generation displays, professional cameras, factory automation, advanced automotive driver assistance, and surveillance systems. "Xilinx is building on its substantial technology and market lead at 28nm with another break-out portfolio at 20nm that is a generation ahead of its traditional competition and offers significant new advantages versus ASICs and ASSPs,” said Xilinx’s senior vice president, programmable platform group, Victor Peng.

There are also development planned for its second generation of 3D ICs with both homogeneous and heterogeneous configurations. High-growth applications include Nx100G/400G smart networks, top-of-rack data center switches, and highest integration ASIC prototyping. This will include two-level 3D interconnect with industry-standard interfaces and 5x greater die-to-die bandwidth as well as four times the transceiver bandwidth up to 56G to support 40G networks.

The 8 series All Programmable FPGAs will provide twice the performance, half the power, and 1.5 to 2x the integration capabilities over the current generation says the company using TSMC's mainstream 20nm process. High-growth applications for these devices include Nx100G wired networking, wireless L1 baseband co-processing for LTE A wireless networks, and next-generation system acceleration and connectivity.

Architectural improvements extend the resource utilization