Xilinx pushes Zynq into defense and aerospace applications

October 29, 2012 // By Nick Flaherty
Xilinx is looking to extend its grip on FPGAs in the defense-grade applications with support for its 7 series and the new Zynq-7000 dual core ARM system-on-chip devices.

The company claims to have 50% of the military and aerospace market for programmable logic devices, bringing in just under 15% of its revenues in the last quarter.
Xilinx is including three out of the four new generation 28nm Zynq parts in the defense range as well as two Artix 7 and two Kintex 7 as well as five Virtex 7 high density FPGAs. These use off-the-shelf reprogrammable devices with full temperature testing and added secure IP and design flows to protect the devices, as well as a 17 year product lifetime.
The Information Assurance methodology and DoD 5000 Series compliant Anti-Tamper Security Monitor IP core (SECMON) form the basis for Xilinx’s aim to remove any single point of failure in systems.
“Xilinx is the only major FPGA vendor offering a distinct defense-grade product line with fail safe heritage,” said Yousef Khalilollahi, senior director, Aerospace and Defense at Xilinx. “In addition to the secure capabilities, the defense-grade 7 series FPGAs and Zynq-7000 All Programmable SoCs offer mask set control, ruggedized packaging with fully-leaded (Pb) content for harsh environmental operation, full extended temperature range testing, long term availability and anti-counterfeiting features.”
An example of a defense-grade application for the Xilinx 7 series FPGAs and Zynq-7000 All Programmable SoCs for secure communications solutions is a device with Single-chip cryptography (SCC) capability with Security Monitor 3.0 IP core for physical design security. SCC combines the functionality of multiple FPGAs into a single device, enabling A&D product developers to reduce SWaP-C of systems through higher levels of integration. The defense IP is supported in the Vivado Design Suite that enables C, C++ and SystemC specifications to be directly targeted into FPGAs, SoCs and 3D ICs without the need to manually create RTL.