The Vivado Design Suite, which took the company over 4 years of development (across more than 500 sofware engineers) to ensure a tight optimization of the synthesized RTL output for the fabric of Xilinx’ largest 28nm FPGAs, is said not only to speed the design of programmable logic and I/O, but also to accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor IP cores.
Senior director of design methodology marketing at Xilinx, Tom Feist who was in Paris to present the new tool (and also to run a Marathon) explained EETimes Europe that although this had required a significant investment, the company was now able to offer a complete synthesis tool suite at a fraction of the cost typically associated with the ASIC design tools necessary for multi-million gate designs. Feist commented that existing tools from third-party EDA vendors were becoming prohibitively expensive for the small and medium businesses willing to take advantage of the high performance and the low non-recurring engineering costs of today’s FPGAs.
Of course, the terms of license would not allow users to design outside Xilinx’ FPGA environment, as it is not Xilinx’ aim to compete head-to-head with the big EDA vendors. But many “ASIC refugees” will appreciate, as Feist jokingly stated, evoking engineers who for cost reasons move their original ASIC intent to an FPGA. Available for only a couple of thousand dollars, the Vivado Design Suite has been beta tested with more than 100 customers and Alliance Program members over the past 12 months, including customers using Xilinx’ stacked silicon interconnect-based Virtex-7 devices. As Feist explained, while a lot of tools blast back the design to the finest grain and then try to stitch things up onto hardware, by designing a modern multidimensional analytic placement engine using state-of-the-art EDA algorithms, Xilinx was able to tune