Vivado Design Suite HLx Editions enable, Xilinx says, an ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms. HLx Editions include HL System Edition, HL Design Edition and HL WebPACK Edition. All HLx Editions include Vivado High-Level Synthesis (HLS) including C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystems, and the full Vivado implementation tool suite to enable mainstream users to readily adopt the most productive and advanced C and IP-based design flows. When coupled with the UltraFast High-Level Productivity Design Methodology Guide, Xilinx claims users can realise a 10-15X productivity gain over traditional approaches. The HLx Edition is available as a no-cost upgrade to the Vivado Design Suite.
The productivity comes, Xilinx says, from all or a subset of the following; 1) C-based design and optimised reuse, 2) reuse of IP subsystems, 3) integration automation, and 4) accelerated design closure.
Unlike tradition RTL-based design where the majority of the design effort is spent in the backend of the design process, C and IP-based design enables vastly superior design reuse to speed creation, rapid design exploration for better micro-architectures, replaces error prone manual C to RTL conversion, eliminates time and errors while integrating C and RTL-based IP, and shortens verification time. Using high levels of abstraction, customers have found that they can quickly get overall better or equal Quality of Results (performance, power, utilisation).
To enable these high productivity flows, the HLx Editions include Vivado HLS, Vivado IPI, LogicCORE IP subsystems, and the full Vivado implementation tool suite. In addition, Xilinx and its Alliance ecosystem are continuously expanding market-specific C libraries such as OpenCV for video and image processing and Machine Learning for Automotive Driver Assistance Systems (ADAS) and Data Centre applications. Xilinx’s LogiCORE IP subsystems are highly configurable, market-tailored building blocks that integrate up to 80 individual IP cores, software drivers, design examples, and test benches. New IP subsystems are available for