Yugo Systems externalises FPGA debug with new hardware

January 28, 2015 // By Julien Happich
For the last 10 years, Belgium company Byte Paradigm has operated as a design centre for high-end FPGA-based systems as well as a provider of test and debug solutions for electronic systems. Under the new company trade name, Yugo Systems, the company is about to expand its offering for FPGA debug and verification.

And together with its new launch, Yugo Systems is announcing a unique FPGA debug solution, Exostiv, claimed to deliver up to 200.000 times more observability at speed of operation than traditional embedded instrumentation solutions.


Exostiv vs. traditional and embedded LA solutions. The numbers show the relative observability provided by each solution.

Frédéric Leens, Byte Paradigm's CEO, comments on the new venture, “For a number of years, we have been actively designing with FPGAs and helping our customers debug their systems, and we suffered the same frustration that FPGA designers typically experience with the limited tools provided by FPGA vendors. “

“Back in 2011, we started to investigate about a new hardware-based debug tools that could improve a designer’s access to FPGA’s internals. Although we had heard about Tabula doing interesting developments then, our research was geared towards improving the visibility of off-the-shelf FPGAs”.

“Typically, designers would want to see as much as possible of their design in operation, in realtime, but today’s embedded debug tools and built-in test are too light, only supporting a few kBytes’ worth of information at a time”, continues Leens.

With Exostiv, the company doesn’t require designers to put aside the FPGA’s internal memory for embedded debug and built-in test. Instead it externalises the analysis through fast access points (configured in-system as dedicated IP) capable of feeding the data of more than 32,000 nodes over the FPGA multi-gigabit transceivers. Transferred through up to four 6.6 Gb/sec lanes to an external memory up to 8 GByte, the data can then be further analysed using the company’s MYRIAD Waveform Viewer, designed to handle Terabytes of information.


Exostiv’s data flow.

In a whitepaper titled “ FPGA verification tools need an upgrade ”, Leens lists the debug limitations (economical or physical) that todays’ FPGA designers have to face, also highlighting the fact that in high-end FPGAs, the logic resources are increasing much faster than the amount of memory,