•  
• EDN Europe MAGAZINE
•  
• Free SUBSCRIPTION
• Subscription Renewal
• View Media Kit

• EDN
• EDN Australia
• EDN Asia
• EDN China
• EDN Japan

EDN Europe's Editor Graham Prophet posts a selection of comments and insights prompted by the many items of industry news and rumour that cross the editorial desk or are gathered on his frequent travels to interviews, press conferences and events around Europe - and further afield - and somehow never find their way to the magazine or the web site, recovering some of the information otherwise lost in the noise level...

Tuesday, March 08, 2011

Oh no, it's back!

| Permalink | Email This | Comments (0) |

| Digg This | Slashdot This | add to Del.icio.us |

You may have noticed that an announcement last week brought back an old friend to the marketing of FPGAs; the ASIC-equivalent-gate ratio. Xilinx chose to quote a figure for this ratio for its new Zynq product (follow this link if you missed the story**).

If you're new to FPGAs since this parameter dropped off the radar, here's what it's about. ASIC vendors may quote logic densities achievable on their devices in terms of low-level logic gates. On FPGAs you form logic functions by configuring logic cells that contain multiple gates, registers and assorted configuration switches. So, a function implemented in a single logic cell might take several, fewer, or many (you won't catch me guessing at an actual number) ASIC gates.

Problem; the equivalence is highly variable, depending on the application, on the particular configuration of an individual FPGA-maker's logic cells, and on the tool that compiles the logic for it, and likely on quite a few other factors as well. As a marketer, you can go cautious on the multiplier you quote, and risk looking as if your product has lower logic capacity than your opposition; or you can pitch the figure higher and risk adverse comment that a given design won't fit in your product when the numbers say it should. Guess which way many of the marketers went? Significant, and rather bad-tempered, disputation followed.

Over time, PLD vendors dropped the figure from their data sheets. Had they been overcome by a sudden flush of responsibility and decided the parameter was more trouble than it was worth? Maybe so. But look at what else was happening; for a long time, with each new generation of PLD that they brought to market, the programmable chip makers would say, “We have brought yet another slice of the ASIC market within our reach,” and the equivalent-gate comparison was a valid selling point.

But recently, that process has come, more or less, to a stop. If you're building a large ASIC today, you have to have some compelling reason to do so (extreme power constraints, outright speed, IP security, whatever) and even the leading-edge FPGAs can't do what you need; conversely, if the big FPGA can deliver what you need, you're not going to embark on the hideously expensive path to an ASIC.

Put that another way; the programmable makers have fought the ASIC into a corner (a lucrative corner, to be sure, for those still in the game); they can't get much further into that corner but the ASICs aren't coming out of it, either: so the gate-equivalence number isn't much use anyway.

Now, Xilinx assures me, its Zynq product once again brings it – sometimes – into a marketing fight where an ASIC solution is an option, so the ratio is back. Probing this issue a little gets a response hinting that not everyone on the Xilinx team necessarily thought resurrecting the gate-equivalence figure was such a great idea; but a spokesman assures me that they have quoted a conservative number for the parameter, that won't have anyone running out of logic cells when the equivalent gates number said they ought to have plenty.

So, in how many projects these days is there really an ASIC/programmable decision point? Or, is the fence round the corner (that I hypothesised above) in fact a clear dividing line?

The comment facility on this thread has been off for a while – because it was getting swamped by spam – but I'll open it for any thoughts you have on this one.

**If you didn't see the story, maybe you are not registered to receive the monthly Digital Edition of EDN Europe? The registration form is here, or click on the "Free Subscription" link above.

Related entries in: Programmable Logic/ Memory |

Post a comment

* Display Name
* Comments
* Anti Spam security code	To pervent spamming, please enter the anti-spam code as shown above to proceed with the submission