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picoChip optimises processor array chips for femtocells

PicoChip has launched a new series of chips to consolidate the leading position it claims in the emerging femtocell basestation market. Describing the PC3xx family as second-generation devices, picoChip says that the chips integrate the company’s modem architecture in a highly-integrated form that will reduce the bill-of-materials cost for femtocell manufacturers, while increasing performance.

Asked if picoChip has, in effect, “bet the company” on the femtocell concept, VP of marketing Rupert Baines replies, “Not really; it would be a setback [if the femtocell concept did not take off] but the architecture we have developed is versatile and we can quickly apply it to other advanced communications standards. At MWC (Mobile World Congress, held in February 2008 in Barcelona), we already demonstrated a single development board running as either a WiMax or LTE basestation with only software changes. But we do not see the femtocell market as likely to falter; it is being driven by the [network] operators via ‘carrier pull’ who see it as a way to reduce their capital and operating expenses while [re]gaining access to lost revenue, and providing a platform on which they can build new services. We have solutions for WiMax, cdma2000/ EvDO, TD-SCDMA and LTE, existing and in development, based on our multi-core DSP platform.”

The first of the new family, PC302, is a single-chip device for HSPA (highspeed packet access) femtocells compliant to TR25.820 and the now-standardised “lu-h” interface. It will support up to four users for residential and small-business users with data rates of 14.4/5.5 Mbps (down-/uplink). As compared to the fully softwaredefi ned approach of picoChip’s PC202 chip, the 302 “hardens” into silicon the features needed specifi cally for a W-CDMA/HSPA femtocell design. It employs hardware acceleration of key features of the standard, and reduces the number of processors in the company’s signature multi-processor array to around 80. The company uses redundancy techniques in the processor array, bypassing a row of processors if any one has a manufacturing defect. Perfect devices become an extra-performance variant that has, effectively, more processor elements than the standard part. In 65-nm technology, the 302 integrates a 3GPP NodeB modem, RNC stack, radio resource management (RRM), network listen functionality, and other peripherals. The software-defi ned architecture of the processor array allows for in-service upgrades, and has processing-power margin to host customer-specifi c functions and other home-networking functions. Power, Baines says, is “around 10W,” and the chip is sampling now, with volume production in mid-2009.

picoChip, www.picochip.com