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Power management in SoCs

Teklatech, a new Danish EDA company, has introduced its FloorDirector floorplanning tool, which attacks power-related issues—especially dynamic power—early in the design rather than at the purely physical level. The twin objectives are to optimise SoCs (Systems-on-Chips) for low power and minimise supply noise. The floorplanning engine analyses the dynamic power signature of every system block and identifies initiators of critical-voltage-drop chains in the design. With power shaping techniques and statistical clock timing analysis, FloorDirector provides systemlevel IR drop solutions while maintaining scalable clock-level synchronisation. You can floorplan a chip for optimal power-peak flattening, leading to reduced dynamic IR drop and hence improving overall signal and power integrity. Dynamic power peaks lead to ground and power bounces, impairing signal integrity and noise margins. Voltage drops and supply noise will lead to unpredictable signal integrity, power integrity and timing effects; mixed-signal SoCs encounter additional challenges due to noise coupling between digital and analogue parts, which degrades RF performance.

Teklatech,
www.teklatech.com