Smallest, lowest-power ARM core ever

ARM targets low-power and mixed-signal MCU applications with Cortex M0 design

With the latest member of its Cortex family of IP processor cores, the M0, ARM has made a further move to capture the “low” end of the microcontroller market. M0, the company says, offers 32-bit performance in the footprint of a 16-bit processor, adding a further incentive to 8-bit MCU developers to ‘skip’ 16-bit devices and move directly to 32-bit, a trend that ARM has been fostering for some time. The M0, when implemented in a comparable silicon process and configured for comparable performance, occupies 0ne-third the area of an ARM7TDMI core – a minimal configuration uses 12k gates – and has processing power of 0.9 DMIPS/MHz, at 80 microwatts/MHz. The core is, in effect, a version of the M1 core that ARM optimised for fabrication on a full-custom platform: M1 is the core that ARM developed for efficient implementation on an FPGA target, that you can configure on, for example, Actel, Altera, or Xilinx programmables. If you run the RTL for M0 through an FPGA-optimised synthesis package such as, for example, Synopsys’ (Synplicity’s) Synplify, is the result an M1? “Definitely not,” says product manager in ARM’s processor division, Dominic Pajak, “It’s a completely new core design at a new low-cost/low-power point, complementing the M3.” The M0 has the programming model of the M1, and is binary-compatible with the M3 that is used in several manufacturers’ MCUs.Pajak emphasises that a key point of the M0 is energy efficiency, having the same dynamic power as a 16-bit core. It will also run at “ultra-low-power” in deep-sleep mode, and with the 32-bit architecture you can perform tasks in fewer cycles, shortening the active period when you do wake it in intermittent applications. The M0 also extends the ARM offering to mixed-signal chips – it is very viable in 180- to 250-nm silicon processes, Pajak adds.

The M0 uses the same development tool chain as the M3, its instruction set comprising “the Thumb ISA plus a few Thumb-2 instructions.” It is also compatible with the Cortex Microcontroller Software Interface Standard (CMSIS), the vendor-independent hardware abstraction layer for the Cortex-M processor series that ARM launched late in 2008. Typical application areas, ARM suggests, could include low-power wireless devices and sensors, ultra-low-power Bluetooth (a.k.a. WiBree), metering and human-interface devices.

Early licensees of the Cortex-M0 processor include NXP Semiconductors and mixed signal ASIC designer, Triad Semiconductor. Geoff Lees, vice president and general manager, Microcontroller Division, at NXP, says that the company will bring M0-based products to market later this year. The company’s experience with the M3 core, he adds, convinced NXP that there was scope to move to a much lower-power product regime; he hints that NXP may move to an all-ARM-based MCU strategy at some point in the future.

The Cortex-M0 processor is supported by the Keil MDK-ARM Microcontroller Development Kit, which integrates the ARM RealView Compilation Tools with the new Keil µVision4 IDE and Debugger. The processor is also be supported by third-party tool and RTOS vendors including CodeSourcery, Code Red, Express Logic, IAR Systems, Mentor Graphics, Micrium and Segger.

EDN Europe