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Programmables for power-constrained designs

Actel has extended its Igloo series of lowpower FPGAs with Igloo Plus; whereas it designed the original devices for maximum density, it optimised the new parts for I/O count. The core logic structures remain the same as in the earlier parts. There are three devices in the family, spanning 30,000 to 125,000 gates with, respectively, 120, 157 or 212 I/Os. They have up to 64% more I/Os per equivalent device than the earlier parts, arranged in four banks. You can hotswap the connections, which have Schmitt-trigger inputs for noise tolerance. As with the Igloo series, they support the feature Actel calls Flash Freeze: you can place the device in a very low-power standby mode that nevertheless holds I/O states, and from which the device can “wake” in 1 µsec. Actel envisages that designers will use the chips for functions such as level shifting, GPIO expansion, address and data-bus multiplexing and decoding, interface translations, and general “glue” logic. The 30,000-system-gate part has a static power consumption of 5 µW, Actel says. Allowing for the I/O orientation of the Plus series, this is up to 16 times lower power per I/O that some competitive devices, the company asserts. The latest release of Actel’s Libero design package includes a “push-button” power-optimisation option, which you use as a postdesign step to reduce power usage. It will, Actel says, have a minimal effect on performance, impacting speed by a few percent at most. Moreover, the tool gives you feedback on which areas of the design use most power; a cycle-accurate analysis looks at peak power per cycle as well as average power over the entire simulation. You can also translate this information into a batterylife prediction. Igloo Plus chips will cost from just under $2 to $4 (250,000).

Actel, www.actel.com.