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Quad-core DSP packs performance and features

The MSC8144 from Freescale packs four StarCore SC3400 DSP cores along with 10.5 Mbytes of internal memory, dual Gigabit Ethernet interfaces that support SGMII (serial gigabit media-independent interface) and RGMII (reduced gigabit media-independent interface), and a 16-bit UTOPIA (universal test and operations physical Interface for ATM). The package also includes a 4×/1× Serial RapidIO interface and 2048 TDM (time-division-multiplexing) DS-0 channels to connect to PSTNs (public-switched-telephone networks) networks. The MSC8144 targets wire-line- and wireless-infrastructure applications for voice, video, and data services. Additional on-chip peripherals include a DDR-I/II controller and a 66-MHz, 32-bit PCI-bus in-terface.

Freescale based the MSC8144 on the StarCore SC3400 DSP core. It includes a number of techniques to support a 1-GHz clock operating frequency. The SC3400 DSP core includes new SIMD (single-instruction-multiple-data) instructions, as well as exception and branch prediction. The SC3400 core includes instructions for Viterbi and video algorithms. Each core has a 16-kbyte instruction cache, a 32-kbyte data cache, and a memory-management unit. The device employs a quality-of-service technique for self-balancing the load. It employs user-transparent L2-cache-port interleaving to improve performance by 5 to 20%. The DMA auto initialization, granularity, and core-offload buffer-chaining scheme reduce the overhead of programming the core and improve memory efficiency, especially with SDRAM. Improvements in the pipeline limiter reduce the performance bottleneck for the TDM bus. The hardware-based background-cache-sweep operation helps avoid core stalls.

Because the SC3400 instruction set is a superset of the SC140 instructions, the MSC8144 software is fully binary- and assembly-code-compatible with Freescale’s multiple- and single-core DSPs based on the StarCore technology. Freescale’s CodeWarrior integrated development environment supports development for the MSC8144. It includes optimizing C/C++ compilers, profiling tools, cycle- and instruction-accurate simulators, device drivers, and operating systems. It comes with a hardware-development platform and reference board design. Enea’s ( www.enea.com ) OSEck RTOS supports the MSC8144, with a pre-emptive and compact real-time kernel. The MSC8144 will be available for general sampling beginning in the third quarter of 2006 in 1-GHz and 800-MHz versions in a 783-pin, 29×29-mm FC-PBGA package for $180 (10,000).