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Reconfigurable processor array meets power challenge

IMEC, the research organisation based in Leuven, Belgium, has announced that its reconfigurable processor architecture ADRES that it has developed for multimedia applications to the point that it is ready for transfer to the commercial world. IMEC developed the architecture to fulfill the need for a flexible processor to handle multiple multimedia standards, with the additional requirements of being completely programmable in C—and of using the same or lower power than a singlestandard, dedicated ASIC solution. The outcome of the IMEC team’s work, according to IMEC researcher Serge Vernalde, has demonstrated that C-programmability is feasible in a portable wireless multimedia product, with a simulated power demand of 17 mW (CIF resolution) or 50 mW (VGA) to decode 30 frames/sec of H.264/AVC content. This implies that a flexible media processor can be competitive with an ASIC solution in power terms. ADRES is a coarse-grain reconfigurable array of processors, the processor elements being specific to an application domain. It exploits parallelism inherent in the algorithm, and operates on data located in close proximity in the processing array—IMEC’s work has demonstrated in the past that moving data to and from memory can be a major source of power inefficiency.

An “instance” of an ADRES processor has a 2-D (N
N) array of tightly-coupled processing elements that runs the data-flow aspects of the application, and a 1-D (linear) VLIW that executes controlflow aspects. The challenge with such exercises is to eliminate hand-crafting of the code, and to efficiently compile applications on to the hardware. The tool flow for the IMEC design takes an architectural description of the particular instance of the hardware— which scales according to application complexity—as one input, together with the application C-code. It outputs fully scheduled hardware-configuration data for the array, including full power control to shut down elements that are not in use at any given instant, and software code to run on the array. The compiler is fully parameterised to scale with the hardware.

IMEC has used the tool flow for multi-processor SoC designs. Scaling a single ADRES is efficient up to a certain point, beyond which you need multiple processors and an NoC (network-on-chip) approach (IMEC has used the NoC from Arteris). The group believes in an approach that exploits an application’s inherent parallelism, based on the designer’s expertise. Over many years, many researchers have pursued the objective of a method to extract and program the parallelism inherent in an arbitratry application— has IMEC proved that that approach is impossible? “No,” says IMEC’s Diederik Verkest, “but we prefer a solution where the designer is in charge, and the tools automate the “bookkeeping” of implementing parallelism.”

IMEC, www.imec.be, Arteris, www.arteris.com.