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Reconfiguring figures in FPGA programmes for 2010

 

Next-generation announcements have appeared from three FPGA vendors over a short period—from the two leaders in the sector, and from a new entrant—and all feature, to a greater or lesser extent, dynamic reconfiguration as part of their strategy to take programmable logic forward to higher densities and throughputs. In each case these are technology announcements, and in each case the respective vendors promise that product announcements will follow later in 2010.

Altera and Xilinx have both announced their plans for chips that will use silicon at the 28-nm silicon process node. The fi rst announcement came from Altera, outlining a strategy to achieve very high throughputs—as much as 400 Gbit/sec per device— for datapath functions in future networking applications. Altera’s 28-nm chips, yet to be named, will feature embedded HardCopy function blocks, embedded 28-Gbit/sec transceivers and a capability for partial reconfi guration of logic functionality while the chips are in operation.

HardCopy is Altera’s migration path for FPGA designs that achieve high volume. A HardCopy part has the same logic architecture as a Stratix device, but without the SRAMbased confi guration logic; Altera programs the logic functionality with a mask step. This yields a function with much higher logic density than the programmable array, but less than cell-based ASIC. In the next-generation parts, Altera will build FPGAs with commonly used functions embedded in the chips to offer higher overall density, improved time to market and lower cost and power. The blocks are most likely to be high-complexity functions that are stable, such as forward-error-correction: the company would not comment on whether a processor core is likely to appear as an embedded HardCopy segment. Altera will use the facility to embed these pre-defi ned functions in its own design fl ow; the company says that it may extend this capability to customers at a later stage.

Also key to building extremely high-throughput parts will be the provision of on-chip transceivers for 28 Gbit/sec speeds. Altera acknowledges that design of printed-circuit boards for such data rates will not be straightforward. “They will likely not be FR4 (fi breglass pcb material)”, a spokesman said, and electrical links at such speeds will be very short, most likely connecting to an optical transceiver, or another Altera chip. The company hypothesises a 400 Gbit/sec throughput FPGA that would have four groups of four-lane, 25-Gbit/sec channels in and out. The last element necessary to achieve the logic density to support data rates of this order is partial reconfiguration.

The ability to change logic functionality on-the-fl y effectively increases device density beyond what process scaling can achieve. Altera has not previously offered a partial reconfi guration facility in its chips. Designers will be able to reconfi gure the device with a granularity of a single LAB, up to large functional blocks, and tool support will mean that they will not have to understand the detail of the FPGA logic to implement the strategy. Partial reconfi guration will take from 100 sec to 100 msec, and I/O lines will remain in a known state while it happens. Altera will extend the facility already present in its Quartus design software, which enables partial re-compilation of a design, to support the feature; it will assist the user with partitioning for partial reconfi guration, but will not extend to analysing a design to ensure correct scheduling.

XILINX MERGES VIRTEX, SPARTAN

Xilinx, meanwhile, focuses on power reduction in its preliminary 28-nm-technology announcement, declaring that its forthcoming—also as yet unnamed— next-generation chips will consume half the power at twice the capacity compared to their predecessors. Having long positioned its parts as alternatives to ASICs, Xilinx is also now targeting functions that today’s designers obtain in ASSPs; complex ASSPs suffer from some of the same cost/performance issues as ASICs when they migrate to smaller process nodes, Xilinx says, and offers the FPGA as an alternative.

In the forthcoming device range, Xlilinx has reunifi ed its product range and will no longer offer the distinct Virtex and Spartan—cost-reduced— product lines, but instead will produce a single series that maintains performance over a broad range of device sizes.

A 28-nm, high-k metal-gate low-power process reduces static power by 50%, and device-level techniques lowers dynamic power also by 50%, Xilinx says; design-tool innovations such as clock gating account for another 20% power reduction. The company also cites its use of reconfi gurable techniques as a means of cutting power by loading only the functions that a design needs at any given time; less logic occupied at any time equals less static power consumed. Xilinx will also use the feature to control I/O power. New releases of its design-tool set will reveal a major effort to “make reconfi gurability easily accessible,” the company says.

The unified architecture will be a clear derivative of the existing Virtex ASMBL approach, Xilinx says, and IP core libraries will transfer to the new parts. Xilinx, like Altera, outlines a 400-Gbit/sec-throughput line card as a possible future product that might use the technology. Also part of the strategy will be the targeted design platforms, offering features and IP for specifi c application domains, that the company has introduced in recent months.

Unifying the architecture leads to “socketable IP” that will allow customers to preserve their IP investments and more easily offer product portfolios that address a broad range of end-market requirements. The new silicon devices and development tools will form the Base Platform for the next generation of Targeted Design Platforms from Xilinx and third parties, and will include what the company terms Ultra-high-end FPGAs; the company takes an approach that will enable very large devices to target some very high-volume applications. By Ultra-high-end FPGAs, Xilinx means chips that integrate high serial-I/O bandwidth, logic density greater than twice that of what is currently in a high-end FPGA, and highbandwidth interfaces to nextgeneration memory technology. This enables telecommunications system developers to replace a single large ASIC or an ASSP chip set for applications such as Terabit switch fabric in telecom systems, or 400G OTN (optical-transport-network) line cards.

Xilinx’s collaboration efforts with ARM on the next-generation AMBA AXI specifi cation with extensions for FPGA implementation, announced in October 2009, will further drive IP development and reuse by providing software and hardware designers with a proven, broadly adopted standard for interconnecting IP blocks and building embedded systems.

Devices will start to become available in the forth quarter of 2010, with initial tool support available in the ISE design suite in June.

TABULA BREAKS COVER

A new entrant to the fi eld is FPGA start-up Tabula (the name derives from the Latin “tabula rasa”, usually translated as “blank slate”), revealing some details of a technology that makes extensive use of dynamic-reconfi guration techniques.

Tabula is not all that new, having been in existence for several years and having built up a team of over 100 people, with what is probably the most extensive start-up funding behind any recent FPGA start-up. It calls its Spacetime architecture a 3D structure, the third dimension being time. Unlike other attempts to employ reconfi guration techniques, Spacetime appears to operate at fi negranularity level and reconfi gures logic within each function on the chip, at gigahertz speeds, in an eight-phase cycle, always loading only the logic that a function needs, just ahead of when it needs it.

This implies—although further details were not available at the time of compiling this article— that the design tool suite is able to look in detail at the temporal behaviour of an application and compile to logicconfi guration patterns accordingly.

In the words of the company’s announcement, “Tabula will leverage Spacetime to deliver 3-D devices that have signifi cant density advantages and dramatically shorter interconnects when compared to FPGAs that use 2-D architectures, while preserving a traditional design methodology. As a result, Spacetime will enable a new class of programmable devices that combines the capability of an ASIC with the ease of use of an FPGA at price points suitable for volume production.”

“The key to Spacetime and its many advantages is resolving the interconnect problem intrinsic to FPGAs,” says Steve Teig, Tabula’s president and CTO. “Almost 90% of the core area of FPGAs is devoted to the implementation and control of interconnect. Besides driving up die size and product cost, the long connections also limit performance and make timing closure more difficult. If you’re going to achieve a breakthrough in programmable capability and affordability, you have to make the interconnect more effi cient, and that’s what Spacetime does.”

Teig says that Tabula will initially target the programmablelogic market but will also extend the benefi ts of programmability into markets that FPGAs cannot serve cost-effectively.

Tabular says that the process of reconfi guration in multiple sequential steps is equivalent to adding extra physical layers in a third dimension; it call each such “virtual layer” a “fold”. Each such fold is a space in which computation and signal transmission take place. Each fold performs a portion of the desired function and stores the result in place. Following a reconfi guration step, the fold uses the locally stored data to perform the next portion of the function.

Tabula says that Spacetime devices will provide signifi cantly higher logic, memory and signal- processing capabilities than FPGAs; relative to 40-nm FPGAs, the claimed improvements are 2.5 times higher logic density; two times higher memory density; 2.9 times higher memory ports; and four times higher DSP performance. Product announcements, Tabula says, will follow later in 2010.

Altera, www.altera.com;
Xilinx, www.xilinx.com;
Tabula, www.tabula.com.