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Secure memory protects FPGA configuration IP

Maxim memory chip paired with Altera Cyclone chips

Altera has recently endorsed Maxim's 1-Wire secure memory devices as a means of adding security to designs using Cyclone III and Cyclone II FPGA families. The secure memory devices incorporate both the Secure Hash Algorithm (SHA-1), a public hash protocol developed by National Institute of Standards and Technology (NIST), and the 1-Wire interface. This combination implements a challenge-and-response authentication scheme that prevents unauthorised cloning of OEM FPGA designs. The authentication sequence distinguishes between an authorised and a cloned environment. An authorised environment or product incorporates a 1-Wire secure memory, which has the correct OEM secret key. Once the FPGA determines that it is communicating in an authorised environment, it transitions to normal operation by enabling all the functions defined by the customer-specific configuration code stored in the SRAM. If the authentication sequence fails, the FPGA can either disable system operation or set system operation to reduced functionality. The 1-Wire bus is a simple signaling scheme that combines data and power for device operation onto a single bus and ground return.
The complete FPGA security reference design is available on Altera's website. For an online presentation of how this security solution works, look here. The memory devices cost under $1.00 (1000).