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Sigma-delta ADC IP block offers programmable resolution

IP (intellectual property) provider Chipidea is expanding its analogue-to-digital converter offering to include a range of sigma-delta cores that provide programmability—in operation— to optimise for either high resolution or low power consumption. You can use the cores in SoC-product designs that will process multiple standards, in bandwidths from 100 kHz to 10 MHz—typically, digitising the output from a radio block in a portable device. Resolution is up to 16 bits, and users can configure the core as a matched I/Q converter or as part of a complete analogue front end. The IP includes programmable decimating filters. Because the ADC is programmable, you can use a single converter to digitise the output from more than one different RF front end. Applications such as DVB-H—according to Chipidea’s CTO Carlos Leme— require a conversion bandwidth of around 4 MHz, which is well within the core's capabilities; the same is true for standards from cellular phones to WiFi and WiMax. The IP is for implementation in standard digital CMOS: the sigma-delta architecture yields good immunity to interference from power supplies and substrate noise. The IP can build a single, stand-alone ADC, a matched IQ-ADC or part of a complete analogue front end; it comes with a PLL for clock generation, plus analogue and digital filters. It is now available in 0.18-
m and 130-nm technologies with 90 and and 65 nm in development. Ease of porting to different foundries is in part due to the switched-capacitorbased architecture. A specified operating point is 4.5 mA current demand, for 64 dB in 3 MHz, from a circuit block measuring under 0.42 mm2—the design achieves programmability without area or power penalty, Leme says. Variants comprise the CI3621tl and CI3621ul 13- to 11-bit, 120-MHz programmable ADC with 200 kHz and 4 MHz BW; and CI3617tn, an 11-bit, 120-MHz ADC with 4 MHz BW.

Chipidea, www.chipidea.com