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SIGNAL INTEGRITY: Eye don't like it

BY HOWARD JOHNSON, PHD -- EDN Europe, 01 Dec 2006



My heart sank when I first saw the hideous jitter and loss of noise margin evident in the eye diagram of Figure 1. The figure shows the received eye diagram for a simple serial connection operating at 2.5 Gbps. This differential link connects a fiber-optic receiver module (O/E) to a large protocol processing chip (PHY). The figure illustrates the signal measured with a high-bandwidth differential probe at the receiving end of the link (Figure 2). Data goes from left to right in the picture.

The layout for this system looks perfect. Both O/E and PHY modules provide easily accessible differential ball pairs at the edges of their respective pin fields. The layout designer wisely chose to keep these short differential traces on the top layer only, avoiding all vias. So why does the eye diagram look so awful? To address that question, you must take apart the eye diagram.

Every eye diagram comprises many small segments of the received signal. Your oscilloscope first captures one segment, then a second, and aligns the timing of the segments bit for bit before superimposing them. The scope continues accumulating segments in this way until, finally, it displays portions of every conceivable bit pattern.

In the complete eye diagram, your most troublesome patterns are very obvious within the eye opening, making them easy to spot. What a great way to check margins in a finished system!

Unfortunately, the eye diagram makes a terrible diagnostic tool. It shows aggregate performance but clutters the picture with an overabundance of useless information, making it difficult to determine which edge causes which artifact.

A step-response test straightens out the clutter. This test repeatedly stimulates the system with just one step transition, preceded and followed by the longest contiguous strings of zeros and ones that you can manage. Use vertical averaging during this test to block random noise. The step-response test pinpoints all artifacts resulting from each individual bit transition.

Figure 1 highlights in red the system step response. This step response reveals an initial rising edge followed by a negative blip, possibly a reflection, centered 400 psec after the midpoint of the main edge. A later column in this series will investigate some possible causes of that blip.

Howard Johnson, PhD, of Signal Consulting, frequently conducts technical workshops for digital engineers at Oxford University and other sites worldwide. Visit his Web site at www.sigcon.com or e-mail him at howie03@sigcon.com.


 

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