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Silicon-proven 3G DigRF, CSI-2 controller and D-PHY MIPI IP

Synopsys has added silicon-proven DesignWare MIPI IP consisting of 3G DigRF controllers and PHY, CSI-2 (Camera Serial Interface 2) host controller and D-PHY to its IP portfolio. The DigRF, CSI-2 and D-PHY solutions enable designers of baseband ICs and application processors to quickly integrate high quality MIPI interfaces into their complex SoCs with less risk. MIPI DigRF v3 is a low-power, low pin-count interface that simplifies the integration and interoperability between the RF transceiver IC and BBIC (baseband IC). The six-pin digital interconnect reduces system cost and lowers EMI (electromagnetic interference) for dual and single-mode 3GPP 2.5/3G mobile terminals. The 3G DigRF IP solution consisting of controllers, dual-mode PHY and verification environments is compliant with new standard specification and enables easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analogue PLL and is developed as a hard IP block to help ensure the integrity of the high-speed clocks and signals required to meet the strict timing requirements of the protocol.

The solution is available in advanced 65 and 40nm process technologies. Implemented by phone manufacturers, camera sensor vendors and image processor suppliers, the MIPI CSI-2 specification provides an efficient low-power, low pin count interface between camera sensors and application processors. To meet the needs of a range of camera sensors ranging from economical low-end to multi-megapixel cameras, the DesignWare CSI-2 host controller is configurable from one to four data lanes for a total throughput of up to 4Gbit/s. Complementing the CSI-2 host controller is the DesignWare MIPI D-PHY, which is a fully-integrated hard macro available as a unidirectional or a bi-directional PHY. The unidirectional configuration is optimised to enable the implementation of a compact and low power CSI-2 host applications. The bi-directional configuration enables a single PHY to support multiple MIPI interfaces, simplifying the development of designs implementing multiple MIPI interfaces such as CSI-2, DSI and UniPro. Delivering up to 1Gbit/s per lane, the DesignWare MIPI D-PHY meets the bandwidth demands of advanced cameras and display peripherals and is silicon-proven on 65nm and 40nm nodes.