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Single-chip FPGAs for LDPC system

Altera has announced that Sumitomo is using its 40nm Stratix IV GX FPGAs in LDPC (low-density parity-check) high-speed measurement system. Sumitomo’s high-throughput LDPC system features an encoding and decoding algorithm that is capable of improving the signal quality in applications that require efficient data transmission. The single-chip FPGA and its integrated 8.5Gbit/s transceivers deliver advanced performance and data rate speeds, and allow the realisation of over 100Gbit/s performance in the LDPC system. The LDPC system achieves a throughput of 132Gbit/s encoding and 24.48Gbit/s decoding using the FPGA. The LDPC system interfaces with a multi Gigabit ADC (analogue/digital converter) and features a Nios II embedded processor. The FPGAs deliver high density, better performance and low power, and provide transceiver and memory interface technology. The high-end FPGAs feature three variants, a non-transceiver enhanced (E) version and two transceiver (GX and GT) versions. The GX and GT variants feature integrated transceivers that provide high system bandwidth with advanced signal integrity.