Synopsys merges IC layout and verification tools

EDN Europe, 11 May 2009

A continuing theme of developments in IC-design tools is that EDA companies combine or integrate successive steps of their design flow. It has almost become a flow in itself; the first stage of that flow is that the need for a particular tool becomes apparent; the industry develops a point-tool to address the need; and users adopt it into their processes. Then, the users find that the new tool, while it may fix the problem the EDA vendors created it for, makes changes that affect other parameters of the design. So they pass the project back to a previous stage to re-work it, and iterate towards an acceptable result. Ultimately, the EDA vendor finds a way of running the new tool’s processing concurrently with the rest of the design flow, constraining it so that it never makes any changes that conflict with the overall design objectives.
Or, in the case of the announcement just made by Synopsys, making IC verification layout checks as the physical design is being created, to ensure that the physical synthesis process cannot lay down any structures that would subsequently fail a verification check. Synopsys has announced IC Validator, which it describes as a design rule checking/layout verification signoff (DRC/LVS) solution for in-design physical verification and signoff for advanced designs at 45nm and below. Designs teams can reduce physical verification time, “by through in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores.” The last of these points relates to features that Synopsys has added to improve the distribution of processing on multi-core machines; as well as fragmenting and parallelising the task where possible, management software will re-allocate tasks to any cpu that falls idle.
The IC Validator DRC/LVS offering is already qualified by an (un-named) chip maker for the 32/28-nm process node. In-design verification, as opposed to ‘implement-then-verify’ can, Synopsys says, eliminate multiple iterations between design and signoff. At 45nm and below, design-rule-sets (the list of geometric checks that the tools must carry out) also grow rapidly – there are already several hundred such rules in a typical set. Sequential design and verification can be slow and may complicate convergence as layout corrections can alter design objectives such as area, timing, and power. In processes with many layers of metal interconnect, the tools must add non-functional metal where there are areas with no interconnect tracks, otherwise, over the depth of the stacked metal layers, the chip can accumulate flatness errors. IC Validator supervises the addition of this metal and checks that it has no adverse effect on chip functionality; it also incorporates ‘smart’ run-time-reduction features such as on-the-fly rule-set reduction.