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Synthesise logic directly from Matlab

Synopsys’ Synphony HLS (High Level Synthesis) solution integrates M-language—the native language of The Mathworks’ Matlab product—and model-based synthesis to increase design and verification productivity over traditional RTL flows, especially for algorithmically intense applications such as communications and multimedia. Synphony HLS creates optimised RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping. In addition, Synphony HLS complements C/C++-based flows by generating C models for system validation and early software development in virtual platforms. Features include an automated flow from M to optimised RTL; synthesis of optimised RTL architectures for ASICs and FPGAs; a rapidprototyping methodology for early algorithm validation; C-model generation for early software development and fast system validation; and unified verification across multiple flows that include prototyping and ASIC implementation.

Synopsys, www.synopsys.com
More details at www.edn-europe.com/article.asp?articleid=3512