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Tabula discloses 4-chip family of novel-architecture FPGAs

Devices at $200 out-perform largest conventional FPGAs, new start-up claims

Since the brief introduction to the company in the last digital edition of EDN Europe (and here), new FPGA market entrant Tabula has released further detail of its product offering, which it positions as a “new class of programmable device” that offers “unprecedented capabilities at a volume price”.
Tabula’s ABAX device is a 40-nm, SRAM-based, FPGA, but one in which the core programmable logic is continuously reprogrammed in a dynamic-reconfiguration scheme to emulate a device that is several times more dense than a conventional FPGA fabric could achieve, at any particular silicon process node. The result, according to CTO and founder Steve Teig, is that for a price point in the $100 – $200 range, ABAX devices can offer, “more capability than the largest devices from Xilinx or Altera.”
The basis for the devices’ operation lies in the fact that the fundamental speed of the programmable gates is several times higher than the typical application’s clock speeds, so the logic can be multiplexed in time and re-used several times in the space of single application-side clock cycle. In its first product range Tabula has used what Teig describes as a relatively undemanding 1.6-GHz internal clock rate and a 200-MHz external clock. This allows re-use of the logic fabric eight times over. One way of thinking of the architecture is that it reconfigures exactly the logic that a signals needs to encounter, at any instant, just ahead of the arrival of the signal, and re-uses that logic on the next (internal) clock cycle. Tabula’s preferred concept is to represent the time-multiplexed logic as being equivalent to multiple physical layers of logic in a 3-D structure. So, in the case of the initial release of ABAX devices, the 3-D structure has eight layers or “folds”. There is, Teig says, nothing special about a multiple of eight; later series of devices with faster internal clocks will have even more “folds”.
The good news about all of the 3-D conceptual view of the devices is that as a user, it’s all hidden from you: Tabula’s tool set makes it all look like a single larger FPGA. Nevertheless, the hidden architecture has a number of benefits, in addition to simply increasing density, Teig says. Visualising the “folds” as extra layers of logic, a signal can reach other layers in the logic – if you think of them vertically in a 3-D structure – faster than it could reach logic gates spread out across the planar surface of a conventional FPGA. This can speed signal propagation and processing; Teig’s proposition is that in nano-metre-scale CMOS FPGAs, throughput is not determined by logic speed but by interconnect, and that the ABAX architecture provides a massive increase in fast, close-proximity interconnections. A signal held in a latch as one fold changes to the next, effectively reaches that next layer of logic, equating to stepping up through the layers of the virtual 3-D structure, and can do so multiple times within the interval of one application-level clock cycles. On average, Teig, says, this means a signal can reach 3.2 times more look-up-tables (LUTs) in a clock cycle than is the case on a conventional FPGA.
A similar phenomenon occurs with RAM; a single-ported RAM in the ABAX structure acts as (in this generation) an eight-port RAM, with benefits for DSP and other signal processing functions. “DSP blocks can run at 1.6 GHz and the rest of a system can keep up,” Teig says, “It’s not a graphics processor [with highly dedicated, function-specific logic] or a cellphone baseband [with an extremely large amount of total logic] but we can do almost anything in between…. There is no need for hard-code microprocessor cores, because a soft core will run effectively at 1.6 GHz.”
The notion of a layered 3D structure goes beyond being simply a means of visualising the architecture; the tool set relies heavily on advanced place-and-route techniques using timing-driven layout and exploiting the short interconnect lines in the logic. The tools don’t “know”, and don’t need to know, that much of the interconnect is a physical mapping of the time-multiplexed logic; they handle the representation of a wire of a given length and propagation delay as if it were metal.
Despite the fact that the core has a great deal of logic being clocked at 1.6 GHz, Teig claims that power, overall, is roughly comparable to a traditional FPGA of similar capacity; lower static power due to a smaller chip trades against higher dynamic current.
Tabula has chosen to pitch its first devices for the communications markets where large FPGAs currently enjoy good market share, with four devices spanning 220,000 to 630,000 LUTs (each with 5.5 Mbytes RAM, 920 I/Os and 48 6.5 Gbit/sec SERDES) and costing from $100 to $200 in volume in 2010. Teig asserts that these parts have equal or better capabilities than any conventional FPGA currently in that market. The technology, he adds, scales down as well as up, “We can, and will, do a $10 part, that will be more capable than any other technology at that price point.” He also believes at that the technology’s advantages improve progressively at smaller process geometries – mainly because faster CMOS will mean a higher clock in the core, enabling more “folds” of logic. “In two or three process generations we will catch and pass [traditional] ASICs.”