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Test & Measurement World: The philosophy of jitter

When Altera began developing its 40-nm Stratix IV FPGA, the company’s engineers faced daunting challenges on many design and test fronts. Dr Mike Peng Li, Altera’s principal architect and distinguished engineer, explained that device-level jitter has to continue shrinking so that you can maintain a BER of 10^–12 at the physical layer while also providing sufficient margin as the UI (unit interval) gets smaller.

To do that, Altera had to support the many different varieties of highspeed I/O that its customers might choose to implement, including multiple generations of PCI Express (PCIe 1.1 and PCIe 2.0), Serial ATA/SAS (3 and 6 Gbps), Fibre Channel (2.125, 4.25 and 8.5 Gbps), 40/100 Gigabit Ethernet, CEI/OIF (6G and 11G), XFI (10G), and SFI/SFP+. Li stated, “Silicon today performs functions like pre-emphasis and FEC [forward error correction] on the transmitter side and adaptive equalization on the receiver side to compensate for environmental changes in the channel. Further, some customers want to improve BER [bit-error rate] to 10^–15 or 10^–17 so they can forgo functions like FEC, thereby potentially reducing power consumption.”

According to Li, one way to improve margin is to minimize transmitter jitter. A key source of that jitter, he said, is the VCO (voltage-controlled oscillator) used in the RO (ring-oscillator) PLL (phase-locked loop) that generates clock signals. The RO PLL approach, he said, is useful because it affords customers great flexibility in programming frequencies. But the RO PLL is limited by its phase noise, which can translate into random jitter. To avoid that, Altera includes on its Stratix IV device an LC-based oscillator for its high-performance PLLs, which offers much lower noise and jitter, on top of RO PLLs. In addition to addressing the challenges of signal integrity, Altera also focused a lot of attention on power-integrity issues: one person of the team handling that aspect noted that “customers can do whatever they want in the FPGA fabric. They can create some very unusual worst-case scenarios with respect to power-supply level, clock frequency, and device program pattern.”

To characterize the high-speed serial transceivers, Altera engineers designed seven types of characterization boards. With these boards, engineers have access to all of the FPGA’s pins, including the power pins that require sources for each of the device’s subsystems. According to Daniel Chow, a senior member of Altera’s technical staff, “Ten years ago, we didn’t understand jitter the way we do today. We didn’t know about TJ [total jitter], RJ [random jitter], DJ [deterministic jitter], PJ [periodic jitter] or ISI [intersymbol interference]. As Fibre Channel and XAUI came online, we began to understand jitter. Mike Peng Li was one of the first to realize that TJ only mattered when you specified BER.”

To measure jitter, Chow and other Altera engineers use an array of instruments such as real-time and sampling oscilloscopes from Agilent Technologies, LeCroy, and Tektronix. In the lab, the engineers also use Agilent spectrum analyzers and BERTs (BER testers) from Agilent and Synthesys Research.

He noted that oscilloscopes measure jitter in the time domain, spectrum analyzers use the frequency domain, and BERTs use the digital domain. Chow employs spectrum analyzers to look at PJ because this jitter component contains frequencies that the instrument can easily display. He also likes using a spectrum analyzer for determining RJ because it measures phase noise and converts the results into RJ. Spectrum analyzers also have a low noise floor, as low as -160 dBm, which Chow likes for measuring RJ over a specified bandwidth.

“RJ is getting quite small,” he said, noting that standards such as those for SFP and SFP+ transceiver modules specify approximately 800 fsec of noise. “For Stratix IV devices, customers can typically expect RJ values between 600 and 700 fsec. In the lab, we’ve been able to measure RJ as low as 400 fsec. Few instruments can measure RJ below 1 psec. Real-time oscilloscopes are getting there.”

With a real-time or sampling oscilloscope, Chow measures DJ, RJ, PJ, and ISI. He measures TJ with a BERT at 10^–12 BER. If all jitter measurements are properly done, the jitter components should approximately equal TJ; but Chow admitted that sometimes, the jitter components don’t add up to the TJ. “These inconsistencies are sometimes due to the instrumentation, which is why we must understand how each instrument derives its jitter results, including hardware limitations.