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TEST & MEASUREMENT WORLD: Achieving PCI Express physical-layer compliance

With the emergence of the PCI Express 2.0 specification, data-transfer rates doubled from 2.5 to 5.0 GT/sec. To develop effective receiver and transmitter tests for this faster rate, you’ll need an understanding of PCI Express specifications as well as knowledge of system architectures, receivertolerance measurements, stress elements, and transmitter PLL response.

In the 1-hour Webcast “Pass PCI Express physical layer compliance testing the first time,” Bent Hessen-Schmidt, vice president of business development at SyntheSys Research, covers these topics and describes trends in jitter- compliance methodology.

Schmidt cites evidence of the difficulties of migrating to PCI Express 2.0: During the first half of 2007, only 10% of 2.5-GT/sec PLL designs failed, while 60% of 5-GT/sec implementations did. He notes that it is important that both the transmitter and receiver in a common- clock PCI-Express design (Figure 1) track the single reference clock nearly identically to prevent clock jitter from contaminating data. He describes using a spectrum analyzer and a clock-PLL analyzer to characterize PLL, contending that the clock analyzer provides better accuracy and repeatability.

Schmidt ends by describing dualport measurements and saying that test methods are evolving to favor the use of sampling instruments as PCIExpress speeds move toward 8 GT/sec, with the concomitant 20-GHz fifthorder harmonics.

The Webcast, which was sponsored by Test & Measurement World, EDN, and SyntheSys Research, was presented live December 11, 2007. You can view the archived Webcast (via a link that you find at www.edn-europe.com/ article.asp?articleid=2047), which provides detailed descriptions of practical jitter-measurement techniques.

Inphi launches 25-Gbps differential Mach-Zehnder driver

Joining Inphi’s (www.inphi-corp.com) portfolio of optical components is the 2514DZ, a 25-Gbps differential Mach- Zehnder modulator driver. This device delivers the differential output voltage and high data rates required for next-generation 40G DQPSKs (differential quadrature phase-shift keying) and 100G optical-communications applications. The 2514DZ driver—with a differential output-modulation range of 4.0 to 8.0 Vpk-pk and data rates of greater than 25 Gbps—works seamlessly with differential Mach-Zehnder modulators from Fujitsu and Sumitomo Osaka Cement Company (SOCC). The input is single-ended, and both input and outputs are internally ac-coupled (dc-blocked). In addition, the device supports clock frequencies of up to 25 GHz and offers output-amplitude control and adjustable eye crossing. As the transmission line rate increases from 10 to 40 Gbps, significant fiber impairments limit how far the signal can be transmitted before regeneration. For the standard Non- Return-to-Zero (NRZ) transmission method, these impairments limit the transmission distance to a few kilometers. Unlike the NRZ transmission method, which transmits one bit of data per symbol, DQPSK encodes two bits of data per symbol, effectively cutting the transmission-line rate in half. Thus, 40G DQPSK systems are less sensitive to fiber impairments than other transmission methods at the native 40-Gbps line rate and can transmit 40-Gbps data well over 1000 km. Future 100-Gbps systems may rely on even more sophisticated coding schemes to encode 4 bits of data per symbol so that 100-Gbps data can be transmitted at a line rate of approximately 25 Gbps. Inphi’s 2514DZ has been demonstrated to work beyond the minimum specification of 25 Gbps and is now being used by leading module and OEM customers worldwide in the development of such a system.