•  
• EDN Europe MAGAZINE
•  
• Free SUBSCRIPTION
• Subscription Renewal
• View Media Kit

• EDN
• EDN Australia
• EDN Asia
• EDN China
• EDN Japan

TEST & MEASUREMENT WORLD: Increasing abstraction makes DFT more effective

According to the latest International Technology Roadmap for Semiconductors, the cost of manufacturing chips is approaching the cost of testing them. Chip quality is compromised in new deep submicron technologies because new defect types are appearing all the time. To cope with cost and quality, semiconductor manufacturers require increasing amounts of DFT (design-for-test) functionality. IC designers will continue to use mainstream DFT methods such as scan, test compression, and BIST (built-in self test), but they will also need new DFT solutions.

Although there is a consensus that higher levels of abstraction will help manage increasing design complexity, DFT solutions are still stuck at the gate and physical levels. Such lowlevel DFT unduly burdens today’s design flows and methodologies because of the strong dependency on the heavy synthesis process. Take, for example, traditional gate-level internal scan. It currently impedes any complete and costeffective design verification and debug process for two reasons: one, because it comes late in the design flow; and two, because gate-level netlists with scan are tremendously complex and very difficult to debug at the gate level.

The idea of moving DFT to a higher level, particularly to the RTL (register-transfer level), is not new. The problem has always been one of providing acceptable QoR (Quality of Results), comparable to that of traditional low-level approaches.

RTL DFT, starting with mature DFT methods such as scan, will be widely adopted when proposed solutions demonstrate both quality and cost-effectiveness, and when they improve existing design flows without disrupting them. A typical RTL-to- RTL internal scan solution should allow both DFT rule checking and comprehensive implementation of scan logic at RTL. This would mean straightforward simulation and debug capabilities of ATPG test patterns, which strengthen design sign-off capabilities before pre-synthesis. RTL-to-RTL scan would also positively impact current IP-based design methodologies. DFT analysis correction and full scan implementation at RTL provide better- quality, reusable IP. What’s more, IP integration will be easier when designers know that IP cores are truly “DFT ready”.

Novel DFT solutions have to cope efficiently with the challenges faced by both the manufacturing testing community and the design community. Designers expect a DFT solution such as internal scan to be non-intrusive, to help solve critical problems in design verification, and to fit seamlessly with the rest of their DFT methodologies such as test compression and BIST.