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The 3D route to system-on-silicon integration : Leti steps up R&D programmes

At its annual research review meeting, the Grenoble, France-based research organisation CEA-Leti described progress in its programmes for 3-dimensional integration of systems on silicon, and presented details of the investment that Leti is making to further expand its work in 3D. Leti, as Director Laurent Malier outlines, now has around 1600 researchers working, “to create innovation and to transfer it to industry”, based mainly on the Minatec campus in Grenoble. Leti’s programmes are split equally between what it regards as its core technology base – micro and nano fabrication and device research – and application-focused work. In fundamental silicon research, it is working on future process nodes and nano-scale fabrication techniques and devices, “But not,” Malier says, “using EUV (extreme ultra-violet lithography) – we leave that to IMEC.” Malier refers to the programme that Leuven-based IMEC is conducting to prepare EUV technology for manufacturing, in association with equipment maker ASML.

As well as investigating alternative means of fabricating devices with dimensions down to 20 nm and even 11 nm – Leti is continuing research into direct-write electron-beam technology to image structures directly on to wafers using many thousands of electron beams in parallel – activities centre on low-power CMOS, and on III-V semiconductor technology. A new area of interest for Leti in recent years is embedded system design, and parallel or massively parallel computing.

Laurent Malier outlined the overall objective of developing a “toolbox” for 3D integration; as well as the techniques needed to assemble and interconnect stacks of wafers, he pointed out the need for a flexible method of partitioning functions in a system that you will build in 3D, to make the best use of the freedom to choose an optimum technology for each partition. Apart from the technology challenges, Malier points out, the cost/performance trade-offs will have to be part of the optimization, and it’s unlikely that a single design flow will suit all applications.

The 3D theme was further explored by programme manager Mark Scannel, who envisaged a time (he implies, in the near future) at which continued scaling is no longer the economic route to further integration. This may be for technological reasons – wiring losses on-chip defeat further device improvements – or for economic ones; Europe, he notes has considerable legacy wafer fab capacity that could manufacture viable 3D products despite being left behind in the move to nano dimensions. Leti, he says, is working on both 3D wafer level packaging, and on a stacked-CMOS approach, In the former, a single package contains multiple dice, with a construction that is a refinement of today’s multi-chip modules; in the latter, third-dimension-thinking begins at the circuit level.

The partitioning aspect of the design needs to take a design that you would, today, design as a system-on-chip and fragment it; major functional blocks and classes of device – MEMS, logic, memory, RF or analogue, for example – are clear boundaries: but you can also divide up a design by those elements which scale when moved into a different technology, and those that don’t; or those where the IP (intellectual property) changes when you re-use it, and those where it doesn’t. You need to design from the outset for this partitioning, and the “toolbox” of generic building blocks has to support that.

A major focus to the Leti 3D programme concentrates on techniques for ever-more-tightly integrated vertical stacks of interconnected dice. Scannel envisages a “silicon mother-board” end-point for this work, in which a base die would carry both individual “daughter” chips, and more complex subsidiary chip stacks. He outlined progress in interconnection techniques for use between the chips in a stack; one topic is direct copper-to-copper molecular bonding. When two dice are bonded face-to-face Wi-Fi or, in some cases, Scannel describes the use of active “interposer” layers between chips – the technique can make interconnections, at room temperature and normal atmospheric pressure, simply by bringing two copper surfaces into intimate contact with each other. Surface preparation is the key to this process, but with very clean and smooth (on a molecular level – roughness of under 0.5 nm) this is a reliable way to form high-density vertical interconnects, Scannel says; the copper layers bond so completely that subsequent inspection cannot find a join-line.

Also complementing work done on the same topic at IMEC, the 3D group has been refining through- silicon-vias (TSVs) that will connect the lower layers of the metal interconnect on one die, down through the silicon substrate, to form connection pads on the back side of the die, ready to connect to the top surface of the next die in the stack, or to a re-distribution layer (RDL). Leti’s process makes electrically-isolated fine-pitch TSVs that are 3 microns wide, and that pass through 15 microns of a thinned wafer, with a copper filling; demonstration processes work with both die-to-wafer and wafer-to-wafer bonding, with a view to ultimately equipping the process for volume production.

With multiple dice being assembled on top of each other, and with (potentially) very large numbers of fine-pitch connections to line up prior to making the layer-to-layer bonds, how can you ensure correct alignment of the patterns on each silicon element? Leti has found that, with suitable conditions, the answer lies in self-alignment. As the video clip shows, the chips will experience significant forces that tend to pull patterns into alignment automatically.

To further extend this programme, CEA-Leti has now opened a complete 300mm fab extension dedicated to 3D-integration applications. Installation of equipment to bring the facility to full operation is scheduled for the rest of 2010. The integration line includes lithography, metallisation, deep etching, dielectric deposition, wet etching and packaging tools. Laurent Malier concludes, “Leti is recognised as a key player in 3D integration R&D and this new line is a vital addition to our continuously expanding 3D capabilities. It also will enable us to offer heterogeneous integration technologies to customers on 200mm and 300mm wafers.”

—by Graham Prophet

CEA-Leti, www.leti.cea.fr/en