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EDN Europe's Editor Graham Prophet posts a selection of comments and insights prompted by the many items of industry news and rumour that cross the editorial desk or are gathered on his frequent travels to interviews, press conferences and events around Europe - and further afield - and somehow never find their way to the magazine or the web site, recovering some of the information otherwise lost in the noise level...

Thursday, April 23, 2009

The future according to Intel

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In a presentation yesterday (22nd April) to media and analysts, Intel revealed a little more about how it sees the near future in a series of “predictions”. One of these says that “Sub-threshold ICs will enable a new class of smart, ultra-low power devices.” In fact, Intel already gave an insight into where it is heading with this, when it disclosed at this year’s ISSCC (International Solid-State Circuits Conference) an attached processor that it described as a reconfigurable, 4-way SIMD accelerator that operates at 300 mV and has a performance/power metric of 494 GOPs (giga-operations/sec) per Watt.
What Intel is describing here is, in effect, a departure from half-a-century of logic design; in this scheme, rather than switching from fully-off (or as near to it as 45-nm transistors can manage) to saturated, or fully-on, to designate 0 or 1 logic states, the individual devices operate at all times in a linear mode. So, when operating from a 300 mV supply, they (to pick numbers arbitrarily) set logic-high to be 200 mV, and logic-low to be 100 mV. Never saturating the transistors saves power, and it speeds the circuit’s operation because you don’t have to wait for the transistors to come out of saturation.
We already do something a lot like that, of course, in the faster serial buses; the drivers for those lines operate in a linear mode, but at the receiving end, you detect the levels they send and with a comparator function decide whether a given level is a 1 or 0 and return to the saturated switching regime.
In the new structure you stay in the linear mode with every logic level a signal encounters as it moves around the chip. So each logic level has, effectively, to maintain the same calibrated recognition of the values that constitute a 1 or 0, without a comparator function. And they have to maintain that calibration geometrically (across the chip), over temperature and over time. No small set of demands, but Intel appears to believe it can be done, and has done it – at least at the demonstrator scale, with its ISSCC chip.

Related entries in: High-Speed Design |

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