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EDN Europe's Editor Graham Prophet posts a selection of comments and insights prompted by the many items of industry news and rumour that cross the editorial desk or are gathered on his frequent travels to interviews, press conferences and events around Europe - and further afield - and somehow never find their way to the magazine or the web site, recovering some of the information otherwise lost in the noise level...

Thursday, May 28, 2009

To bravely go (reconfigurably)

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I just posted a news item about a new – well, new-in-public, the company has been working on its technology since 2005 – IP company called Akya. It’s offering re-configurable logic for incorporation into ASSP/ASIC designs, or even as the basis for complete chip designs.
It has to be said; this is an area which has seen more than its fair share of crash-and-burn attempts at product launches. And to be fair, the founders of Akya seem well aware of the quicksands which have swallowed other adventurers who have set out on the same quest. There was, to name but one, LSI Logic’s Liquid Logic, that proposed dropping a block of programmable logic into an ASIC.
But that, and others in a similar vein, fell into the trap – according to Akya – of working with an architecture that was too fine-grained and too general-purpose to deliver the potential benefits of processing efficiency and low power.
Just dropping in a bit of FPGA doesn’t work; even the best FPGA architectures are so area-inefficient compared to contemporary standard-cell libraries that if you add enough FPGA to do any thing useful, you make an unacceptable impact on both area and power of the whole chip.
The Akya concept enters the market at a time when fewer and fewer design teams can contemplate SoC custom silicon at all – even some of the big semi houses are said to be finding it tough to get the production volumes to justify some ASSP part numbers.
So if the add-some-reconfigurable-stuff approach has really found a viable expression this time around, it may be that enabling one excursion through the chip-design-flow, to yield several part numbers, will be what makes it work.

Related entries in: EDA/ IP | High-Speed Design | Processors/ Software/ Tools | Programmable Logic/ Memory |

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