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Tools accurately simulate noise in mixed-signal ASICs

IN APPLICATIONS REQUIRING HIGH PRECISION, GETTING NOISE ESTIMATES RIGHT MEANS UNDERSTANDING BOTH THE APPLICATION AND THE TOOLS.

In some capacitive-sensor applications, the ability to obtain noise levels as low as 10 aF (attofarad) rms in capacitive sensor- interface ASICs is critical to high performance. To achieve such low noise levels, a mixed-signal-IC developer must have extensive knowledge of sensor characteristics, as well as an ability to accurately model the sensor- IC interface. Developers must use a topdown method, modeling each sub-block at a high level to meet overall systemperformance requirements. Developers use simulation tools for this task, and the selection of those tools depends on the level in the hierarchy, ensuring an efficient design process.

To achieve low noise levels, developers must vigorously examine and extensively verify the models that the foundry supplies. Developers must have precise knowledge of the simulation tool and its limitations, too. A knowledgeable mixed-signal-ASIC-development group also uses silicon-validated IP (intellectual property). A large portfolio of high-resolution sigma-delta converters; low-offset, low-noise amplifiers; and stable voltage references provides a basis for future designs and offers confidence that ASICs will meet required performance.

SENSOR-INTERFACE ASICs

An architecture for a capacitive-sensor-interface IC performs a measurement of the sensor capacitor, C_S, and the related reference capacitor, C_R, and can produce data for several input configurations, such as C_R/C_S, C_S/C_R, or for differential capacitive sensors, ΔC/∑C (Figure 1). This ability to produce different data can be useful because the effect of stray capacitance decreases for some configurations and improves linearity for others. Designers measure the external capacitor using a second-order, 16-bit delta-sigma ADC. The input interface employs a switched-capacitor technique that merges the external capacitor to sense with the first stage of the delta-sigma modulator (Figure 2).

A quick examination of this circuit shows that the digital output of the modulator is an image of the ratio C_R/C_S. This type of interface is most appropriate for capacitive MEMS (microelectromechanical-system) sensors, which often produce only a small capacitance change over their full range.

A quick examination of this circuit shows that the digital output of the modulator is an image of the ratio C_R/C_S. This type of interface is most appropriate for capacitive MEMS (microelectromechanical-system) sensors, which often produce only a small capacitance change over their full range.

For example, a MEMS capacitive accelerometer produces only a 200-fF full-scale change in capacitance for a 1g acceleration. To achieve system requirements, these tiny input levels often demand that the noise level of the interface be on the order of 10^-18F. Simulation is essential at the start of the design to ensure that developers can meet these goals. One main challenge of this approach is predicting the final, obtainable resolution. Note that targeted figures are in the range of attofarads root mean square. A second major difficulty is sizing the various elements in the design.

NOISE SOURCES

The output noise of the measurement chain determines the final resolution. The sources of output noise come from both the quantization of the ADC and the thermal noise of electronics, including the sensor. The quantization noise depends on the delta-sigma-transfer-function coefficients and on the amount of postfiltering that the decimation filter provides. The oversampling-rate-ratio coefficient controls this second contribution. Depending on resolution, the oversampling-rate-ratio coefficient can be fixed at 128 to 1024. An additional difficulty that may arise early in the design is that some transfer-function coefficients are not fixed but depend on the sensing element itself.

Thermal noise comes predominantly from inside the first modulator stage. The main sources are switches and the operational amplifier in the first integrator. Because the deltasigma converter uses sampled-data techniques, the converter aliases the sources of noise around the sampling frequency of the system. This aliasing in effect transforms the thermal noise of the resistance of switches to classic kT/C noise, where k is Boltzmann’s constant, T is the temperature, and C is the capacitance. The same effect aliases the op amp’s wideband thermal noise around the sampling frequency, but some gain depends on the sensing element (Figure 3).

SIMULATING SENSOR INTERACTION

To evaluate the system’s ultimate performance, it is useful to undertake a system-level simulation with The MathWorks’ (www.mathworks.com) Matlab using the parameters of the secondorder modulator and the sensor. The example in Figure 4 uses a MEMS accelerometer. The model can also incorporate nonideal behavior, such as sampling jitter and operational-amplifier noise. This top-level approach ensures the most appropriate architecture for the system and allows some upfront experimentation with the basic parameters, modulator order, and sampling rate.

You can use any of several approaches to evaluating output noise and final resolution. The approach that is easiest to understand consists of performing manual calculations. However, developers must cross-check this approach with simulations to validate the system. Developers can use popular tools, such as Matlab, or simpler programming languages, such as C++ or Visual Basic, in this system-noise simulation. Visual Basic inside Microsoft (www.microsoft.com) Excel works well as systemnoise- simulation tool because it is available on most computers and allows for easy postprocessing of simulation results.

The simplest method is to simulate the delta-sigma system with difference equations (Reference 1 and Figure 5). For instance, you can model a sampled-data integrator with one simple equation, V_OUT(NT)=V_OUT((N-1)T)+V_IN(NT), where V_OUT is the output voltage, V_IN is the input voltage, N is a variable, and T is the period of the sampling frequency.

Designers add three levels of detail to the simulation model to perform noise simulation in this system: quantization of the ADC’s noise, the sensor’s and reference capacitor’s kT/C noise, and the op amp’s thermal noise. You inject thermal Gaussian noise using the sum of 12 uniform random numbers, which you create in the RND() function of the programming language. This process is simply an application of the centrallimit theorem, which states that the sum of many independent random variables tends to be distributed according to one stable distribution among a small set. The Visual Basic function for producing Gaussian random numbers is simple (Listing 1).

Figure 6 shows noise simulation using different oversampling ratios with the three components of noise. When high resolution is necessary, the main source of noise is thermal noise, primarily from the operational amplifier. Using this tool, designers can determine the oversampling-rate-ratio coefficient, transfer-function delta-sigma coefficients, reference-capacitor size, and maximum total amount of input-amplifier noise that are mandatory to reach a given noise floor or resolution. Using these values, designers can also derive other key parameters, such as sampling frequency, power consumption of the modulator, and the op amp’s bandwidth and integrated input noise. Once the design team freezes the architecture, the transistor-level design can begin with a top-down approach. Noise simulation now moves to the transistor level.

TRANSISTOR-LEVEL SIMULATION

When starting to design an ASIC using a new process, it is important to check for well-modeled noise at the transistor level. Developers must be able to design low-noise structures with low power consumption. Therefore, they commonly use MOSFETs in a weak-inversion operating region, in which the gain of the transistor reaches a maximum value and the noise is low with a minimum amount of biasing current. However, the Cadence (www.cadence.com) Spectre simulator with standard Bsim3 (Berkeley short-channel-insulated-gate-fieldeffect- transistor 3) models often underestimates noise in this region. Therefore, you can use a small test bench to compare simulation results with those obtained using manual computation (Figure 7).

You can use differential pairs comprising two MOSFETs biased in weak inversion with large width and length and small biasing current. For example, each transistor has a current noise of 25 µA and a load of 20 kΩ. When bias is in this weak-inversion region, the MOSFETs’ current-noise density is due only to shot noise. Manual computation of the total output-noise density yields (VN0)²=4qI_CR²=6.4X10-15V²/ √Hz, where VN0 is voltage-noise density, q is charge, I_C is the transistor current, and R is resistance.

Using the standard parameters of the given process with Bsim3.2 models for thermal noise, the Spectre simulator yields an output noise of only 3.3X10^-15V²/√Hz. By switching to Spice thermal noise, however, you can recover the handcomputed result (Figure 8). You must then check the parameter noimod to determine whether the manufacturer or the foundry partner has modified the Spice model and carefully check the flicker-noise modeling of the transistor in the process. This verification is necessary to ensure that flicker-related parameters are present in the parameter set of each transistor. After you have verified that the parameters are there, you should benchmark the flicker-noise results against results from other processes to check whether they are realistic.

CIRCUIT SIMULATION

Cadence tools, including Spectre, are appropriate for the design of analog- and mixed-signal ASICs to perform electrical and noise simulation. You can use classic noise analysis to evaluate, for instance, the op amp’s integrated noise of the operational noise. To improve the amplifier’s low-frequency noise, you can add chopper cancellation to the input stage to remove both flicker noise and offset. Classic noise analysis cannot predict the final output noise in chopper-stabilized designs, however. Therefore, designers use the periodic-noise analysis of SpectreRF to predict the noise at low frequencies (Figure 9). Using this simulation, you can establish that integrated noise is 30 µV over a 1-Hz to 1-kHz bandwidth without the chopper. With the chopper enabled, periodic-noise analysis shows a reduction to 2.3 µV. This analysis is efficient and is an important tool for securing final results.

You can also simulate the aliasing effect due to sampling using the SpectreRF option with periodic-noise analysis. To obtain solid results, however, you must compare the system’s bandwidth with its sampling frequency. For instance, consider the basic effect of sampling an input signal in a capacitor (Figure 10). When the switch is closed, this small system is equivalent to the circuit in Figure 11, where R is the onresistance of the switch and C is the sampling capacitor. The system is a lowpass filter with a cutoff frequency of ½π/RC. The total integrated noise is the well-known kT/C noise.

You can illustrate the fact that one-half of the integrated noise is below the cutoff frequency and the other half is above (Figure 12). After sampling, the noise is equally distributed into dc to f_SAMPLE/2 bandwidth with a density of 2 kT/C/f_SAMPLE. For instance, a resistor with a value of 10 kΩ and a capacitor with a value of 10 pF combine with a sampling frequency of 100 kHz to yield a cutoff frequency of 1.4 MHz. Total output noise, VN², is (kT/C)=4X10^-10=(20 µV)², and noise density, VN0², is [kT/(C F_SAMPLE/2)]=8X10^-15=(90 nV/√Hz²]. This result means that accurate periodic-noise simulation of this small system must take into account at least 10 times the bandwidth of the system, even if the sampling frequency is comparatively low. In this case, you would need to use powernoise analysis over a 20-MHz bandwidth.

To illustrate the importance of this point, examine the simulation results of noise density of the sampling capacitor with 1-, 2-, 5-, and 20-MHz bandwidths of analysis (Figure 13). Using the time-domain mode of analysis for the simulation yields a theoretical noise density of 8X10^-15 nV²/ Hz. Manual calculations find noise analysis with a bandwidth of more than 20 MHz. Hence, to obtain reliable results, the bandwidth analysis should be 10 times the system’s cutoff frequency. You must always use manual computations first and then compare the results of those computations with simulation results. With this method, you can have confidence in the noise-simulation results of the modulator input stage.

Using this approach, the simulated noise matches well with actual silicon measurements, which show a high level of performance (Table 1). Using the capacitive-sense circuit with a MEMS pressure sensor would give the system extremely fine pressure resolution (Figure 14). Note that resolution of 1 Pascal is equivalent to the change in pressure of a 10-cm increase in altitude. The combination of manual computation and simulation can accurately predict the behavior of sensing-interface ASICs. You can carry out high-level modeling with difference equations in Visual Basic or C++ highlevel languages and perform electrical-noise simulation at the transistor level with an RF simulator—even if the frequency of interest is near zero. Manual computation skills and experience in the application and technology are also key factors for development success. New design techniques and architectures mean that noise performance of better than 10 aF rms is now possible.