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Trading pieces: IP market grows, but slowly

THE MARKET IN TRADED IP FOR INCLUSION INTO SYSTEM-ON-SILICON CHIPS UNDERPINS MANY OF TODAY’S LARGEST DESIGNS. IT’S NOT THE VIBRANT BAZAAR THAT ITS PROPONENTS ONCE ENVISAGED, BUT THE MECHANISMS FOR IP EXCHANGE ARE EVOLVING, AS WAS EVIDENT AT THE IP07 CONFERENCE IN GRENOBLE.

The concept of an open market in IP (intellectual property) functional blocks as components for use in the construction of system-on-silicon ICs became established around ten years ago, or rather more if you were involved with the idea from its very beginnings. December 2007 saw the tenth running of the IP conference hosted by Design and Reuse (www.design-reuse.com) in Grenoble, France, providing an update on the IP market.

A decade ago, expectations of how the market would develop were somewhat different from how it has evolved in practice. At that time, notions such as the “virtual corporation” seemed attractive. The chip-design process would develop to be more mechanistic and less of an art; small groups of entrepreneurs with a product concept would be able to buy all of the IP functional blocks they required, on the open market. They would contract service companies to build the SoC (System-on- Chip) that would be the heart of their design, enabling them to bring advanced products to market with almost no conventional company structure.

The reality in 2008 is somewhat different. The IP market exists, but not on anything like the scale that the visionaries of the late 1990s hoped. The continuing scaling of semiconductor fabrication into nanometre technologies has had several effects. The chip-design process continues to be something of an art, with EDA tools always following just a little behind process technology. The same Moore’s Law progress has multiplied the engineering cost of bringing an SoC to fruition many times over so that today, a large SoC design can recover its costs only if it sells in very large volumes, limiting the markets that chips in the ASIC mould can serve.

In 2008, therefore, the companies trading in IP blocks are, most frequently, not small teams in virtual corporations, but the major semiconductor and design houses with familiar names. And the economics of big-chip design dictate that in many cases, the IP blocks they purchase are as likely to find their way into ASSP designs and catalogue parts as they are into single-customer ASICs. Nevertheless, the underlying concept of re-use of major functional blocks has become established practice, and the IP07 conference charted progress in the field.

ANTIFUSE MEMORIES ARE SECURE

Craig Rawlings, director of business development at Kilopass Technology (www.kilopass.com), and Steve Cliadakis, vice president of sales at Sidense (www.sidense.com) were both promoting their IP for highdensity, secure memory for storage of on-chip data. With detail differences, both are in broadly the same technology space: using antifuses as bit-programming elements. You may know Antifuses as FPGA programming elements, for example in Actel’s (www.actel.com) products. Rawlings describes how Kilopass uses the antifuse as a one-time-programmable memory. Security comes from the fact that the antifuse is extremely small, that it is a vertical structure and that it is buried deep in the chip. If a hacker tries to decode such a memory, fi rstly he has to locate the structure, and then, Rawlings says, it is very hard to tell a 1 from a 0 by examination. You can store keys, confi guration data and calibration constants; although the memory is writeonce, it takes up so little space that you can provide excess capacity and use it in a write-once-and-abandon mode. The antifuse is immune to soft errors, Rawlings adds, and Kilopass has demonstrated it down to 45-nm technology. The company sells hard IP as a fi xed memory block, in sizes from 16 bits to 1 Mbit—the most popular size appears to be 8 kbit, Rawlings says.

 

One analyst who has followed the statistics of the sector over many years is Gartner Group (www.gartner.com) vice president Jim Tully. He presented a concise history of the subject leading up to an assessment of the present market position. Building a business in IP sales, Tully observes, has been difficult; a protracted sales process involving extended evaluations and a great deal of vendor/customer interaction, with many contractual issues, has led to a time-to-revenue for vendors of almost 10 years, especially if a royalty-based business model is involved. Nevertheless, the SoC market has evolved, and Tully estimates that in 2006 it was worth over $1.3 billion—with ARM (www.arm.com) being by far the dominant player in the field. Standards-based IP has taken on a greater significance, and the overall business model is maturing. There are, however, far fewer designs, and Tully notes the on-going trend toward consolidation in the sector, citing MIPS’ (www.mips.com) acquisition of Chipidea (www.chipidea.com), Synopsys’ (www.synopsis.com) of Mosaid, Gennum’s (www.gennum.com) of mixed-signal IP designer Snowbush, and many more. An associated trend is that he expects an increasing interest in licensing of larger and larger IP offerings, and complete subsystems. Consumer products dominate the IP scene, with demand for fast turnaround of complex designs that—despite their high up-front costs—enter their respective markets in a speculative way, with only a small proportion succeeding and becoming “hot products”. A further trend is that technology—as opposed to design—IP licensing will be increasingly significant, typified by the activities of Rambus (www.rambus.com). Tully estimates that this sector—distinct from the design-IP market value—is worth a further $440 million today. The IP model, he concludes, is here to stay.

IPEXTREME ADDS MOTOROLA CLOCK SYNTH

IPextreme (www.ip-extreme.com) bases its business model on packaging and re-selling IP blocks from “big name” semiconductor houses—for example, National Semiconductor (www.national.com, Freescale (www. freescale.com) and Infi neon (www. infi neon.com). The company, says CEO Warren Savage, now has a portfolio of around 40 IP “titles” and expects to add more at a rate of around ten each year. Its approach is to provide a distribution and support structure for the IP: it takes the blocks from their originators and presents them in a standard package that includes the source code, documentation, integration tests, EDA scripts plus any relevant software and drivers. The catalogue includes a number of processor cores (ColdFire, Power Architecture, TriCore) and automotive functions. SoC (Systemon- Chip) is not the only target: Savage says that the company has sold a ColdFire core for implementation into a large FPGA. The latest addition is from Motorola (www.motorola.com; the semiconductor- research arm that remained with Motorola, as opposed to Freescale): a multi-reference clock generator that will replace phase-lock-loops. One MRCG will replace several PLLs and will be economic for two to three PLLs. The core is a digital clock synthesiser that you can program dynamically, with completely deterministic behaviour: you load a value, wait a specifi ed interval, and the output changes accordingly, with no glitches or other artifacts. The circuit synthesises the digital output using a digital-to-phase converter to set the transition time. PLLs, IP Extreme says, don’t scale with semiconductor-process-technology changes whereas this topology does. It will cover 2 Hz to 1 GHz and can carry out integral de-skewing by adjusting clock-edge timing.

 

A different perspective on the state of the IP-design process came from Ron Collett of Numetrics (www.numetrics. com), who claims to have tracked over 1000 chip-design projects. He concurs that the re-use model is working but finds that in the face of increasing design complexity, designer productivity—although improving—is not keeping pace, with the result that design-team size has doubled since the year 2000. If Collett’s data is accurate, the industry’s planning and estimating is very poor: more than 85% of chip projects miss their scheduled completion dates, with an average overrun of 44%. Collett’s data also analyses the non-linear relationship between the percentage re-use of a given function and the costs of that re-use. If a function is 100% re-used—meaning no significant changes—it will still require nearly 10% of the effort it took to design it, just to integrate it into a new SoC. At 50% reuse— alterations to half of the transferred IP—it is “almost worth re-designing the function.” You need to be achieving 80 to 90% re-use of pre-existing IP to have the process work for you, Collett concludes. “Expectations of the benefits of re-use far exceed reality: [however] increasing re-use greatly increases your productivity relative to industry averages.”

There was also a discussion on “star” IP—including the question “Are CPUs the only stars in IP?” (a reasonable question given the commanding presence of ARM and MIPS in the sector) that did not quite get a straightforward “yes” for an answer but confirmed the role of processor IP. However, the ensuing discussion pointed to the need to develop energyefficient solutions and, in that context, the likely expansion of multicore IP offerings, possibly bundled with dedicated operating-system features.

FORMAL CHECKING OF FPGA SYNTHESIS

A renewed interest in formal verifi - cation as a means of validating the SoC (System-on-Chip) design process appeared with the launch of OneSpin Solutions’ (www. onespin-solutions.com) 360 ECFPGA equivalence checker. As the name implies, this tool is optimised for the logic structures of FPGAs; it was previously an option for the company’s ASIC-checking product. It is, according to managing director and CTO Dr Wolfram Buttner, the only such tool that can handle the sequential optimisations that FPGA tools carry out, such as pipelining and retiming. As with other equivalence checkers, it verifi es that the functionality of a block of logic is unchanged when the logic itself has gone from one stage of design to another, for example synthesis from RTL to netlist. The tool costs 27,600€ for a single-vendor licence, or 38,400€ for a multiple-vendor licence—vendors available being Altera (www.altera.com) and Xilinx (www.xilinx.com). In one of IP07’s conference sessions, the topic of IP quality turned to verifi cation; Dr Buttner expressed the view that in this respect, “the highest quality IP is available for anyone who needs it and is willing to accept the change [in verifi cation methodology].”

 

Other sessions in the open-panel thread of the conference considered issues such as standards-based IP, which in turn diverted into consideration of mixed-signal and analogue IP, and of how one could apply any form of common standards to that sector. Synopsys’ product marketing director Navraj Nandra spoke about a number of process-technology issues affecting analogue, as process dimensions scale down—running mixed-signal circuitry at 0.9V, for example—and observed that when designing in mixed signal, having designers who fully understand the chip’s application domain is essential. Comments in this thread included: “It comes down to having good Spice models, and today’s models are very good.” (Navraj Nandra); “There is a concern in analogue that the basic rules that have held for 25 years may no longer work.” (Sergio Kusevitzky, vice president of business development, MIPS/Chipidea); and “Digital technology, and using a statistical approach, can compensate shortfalls in analogue [performance].” (Bob Tait, product marketing manager, Silicon and Software Systems; www.3sgroup.com).

RAMBUS BIDS FOR 1-TBPS LEADERSHIP

Rambus (www.rambus.com) has launched a campaign it is calling the Terabyte Bandwidth Initiative, aimed at providing that amount of bandwidth to a single SoC (Systemon- Chip) chip. The initiative is a Rambus technology-development program, and by discussing the principles now, the company hopes to begin a conversation in the industry about how such data rates might be achieved—and, of course, hopes to infl uence thinking in the direction of its proposed solution. Marketing vice president Tim Messegee says that he company has already demonstrated three key advances over current state-of-the-art technology that he says will take data rates to the 1-Tbps rate. These are: a 32x data rate (current multiples are to output data at 16x the reference clock); speeding up the command and address bus; and the use of fully differential signaling across the memory architecture. The second of these advances uses a scheme Rambus calls FlexLink, which serialises the command and address bus, with multiple lanes if necessary, mirroring the same—earlier—change on the signal lines. Even if accepted, Messegee says, it will be “several years” before we see any such designs in service: the company introduced its proposal for XDR in 2001, in 2003 customers designed it in, and products appeared in 2005. Rambus has, however, produced test chips that demonstrate each of these three attributes in today’s silicon— and on FR4 PCB material, with wirebonded memory chips, showing that designers will not require any exotic assembly techniques when the time of 1 Tbps arrives.

 

A session on “Implementing security of on-chip resources” provoked one of the livelier discussions of the conference. Panelists identified a number of distinct classes of security problem. One issue is restricting access to the data that the chip processes, and holds, at any given time, such as media content subject to digitalrights management. A second problem is data permanently stored on the chip, such as encryption or decryption keys; while a third concern is the issue of protecting the IP itself against theft, cloning or other unauthorised use. Gagan Gupta of ARC suggested solutions that flow from the ability to construct custom processor configurations: the designer can conceal key items of data where they cannot be found by a memory scan, for example. Or, when you have control of the processor’s instruction set, you can use operations that you do not document to the outside world. An intruder might dis-assemble the chip’s programming, but, “There is no way to work out what each op-code actually does.”

SYNOPSYS MAKES NIOS A CATALOGUE CPU

As if to prove that IP belongs interchangeably to the FPGA environment just as it does to SoC (Systemson- Chips), and having recently announced a package that provides a means of putting ARM Cortex M1 cores into its FPGAs, Altera (www. altera.com) has now co-operated with Synopsys to take some of its own IP in the “opposite direction”. Synopsys will add the IP for Altera’s NIOS II processor core into the DesignWare Star library for synthesis into ASIC designs. Altera claims that the Nios II processor core is the most widely used FPGA-based processor. Synopsys will provide a confi gurable, fully synthesisable version of the Nios II processor core optimised for ASIC implementation in any suitable foundry and process technology. The synthesisable version of the Nios II processor core will be available from Synopsys in the fi rst quarter of 2008.

 

Steve Cliadakis of specialist memory-IP vendor Sidense (see sidebar “Antifuse memories are secure”) addressed the topic of storing secure data on the chip. Along with other contributors, he cited the example of HDCP (high-bandwidth digital-content-protection) keys. Apart from the fact that if keys are compromised, the issuing authority can revoke them—resulting in equipment that does not work— there are also stringent financial penalties for companies responsible for loss of security. Mask ROM and conventional poly or metal fuses represent rather poor levels of security, being readable by optical inspection with a microscope; even charge storage technologies such as flash or EEPROM are vulnerable to having their stored data discovered if the hacker has access to sufficiently sophisticated equipment.

Mike Bursell, European technical manager at Certicom (www.certicom.com) spoke on the subject of cryptographic techniques and noted that cryptography is moving from software into hardware, with co-processors handling the process at increasingly complex levels: first the mathematical primitives, then algorithms, and finally complete protocols. The prevalence of cryptographic resources at intra- and inter-chip levels allows you to protect, he suggested, not only the data that the chip is handling, but also the IP in the functional blocks. You can arrange that a block will only work when you use it with a valid key, and you can deploy such a key at a number of different stages—manufacturing, packaging, or distribution— to protect the IP against hacking or cloning. Bursell cautioned, however, that you cannot make the assumption that that which is secure today will be secure tomorrow; new techniques and more powerful processing resources also come to the aid of the hacker, and “data doesn’t stop being sensitive in X months’ time.” However, 50 kgates enables AES (triple- DES) encryption, and, “when encryption becomes an integral part of the chip, new things become possible.”