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Ultralow-cost, two-digit counter features few components

The ultralow-cost, two-digitcounter circuit in Figure 1 represents an attempt to reduce the number of components using an approach largely based on software and a low-cost microcontroller, the PIC16F84A. The circuit lacks the current-limiting resistors that normally connect to a sevensegment LED display’s pins because a software routine lights only one of the display’s segments at a time—first in the 10s display and then in the units display. Doing so keeps the circuit’s maximum current consumption at a nearly constant level, even if you add a third LED display to implement a three-digit counter. The circuit also lacks digitselection switching transistors that classic multiplexed circuits’ switching transistors typically use, and the circuit includes one common-cathode and one common-anode display. The reason for this approach is that each of the microprocessor’s I/O Port A and Port B lines can assume one of three states: high, low or floating (high impedance). Programming a line as an input places it in a high-impedance state, which turns the display off.

In addition, the program drives only one segment at a time, according to the following procedure: To drive the 10s display, program the line RB0 output and drive it high to light the corresponding segment of the commoncathode display and then program RB0 as an input. Repeat this procedure for lines RB1 through RB6. To drive the units display, repeat the process while applying a low output from RB0 to drive the common-anode display. Figure 2 shows the circuit’s timing diagram. The prototype display uses Kingbright’s (www.kingbright.com) SC52-11EWA (DS1) and SA52- 11EWA (DS2) high-efficiency, sevensegment displays that emit 2000 to 5600 cd at a forward current of 10 mA. At a forward current of approximately 5 mA, the displays remain readable.

Early motion pictures displayed at an 18-Hz rate, which produces marginal flicker. The software executes at a rate of 180 Hz, or 10 times the minimum flicker rate. Each of the display’s seven segments must illuminate for an interval of 1/(1807) sec, or approximately 0.8 msec. To simplify the timing routine (section Delay3 of Listing 1, available at www.edn.com/060817di1), the software uses a refresh interval of 1 msec.

Although this approach provides adequate segment-drive current, the display’s internal LEDs carry a 3V maximum reverse-voltage rating. Driving any I/O line high applies forward bias to one segment of the commoncathode digit but applies reverse bias to the corresponding segment of the common-anode display. The 16F84A requires a minimum of 2V for operation, and thus the circuit must operate in a 2 to 3V power-supply range. The assembler source code in Listing 1 counts from 0 to 99 sec and serves as an unoptimized proof-of-concept software test bed for the display.